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mirror of https://github.com/RPCSX/llvm.git synced 2024-12-25 13:35:39 +00:00
llvm/lib/CodeGen
Bill Wendling 3dc9b4872b LLVM puts padding bytes in the __gcc_except_tab section after the
GCC_except_table label but before the Lexception, which the FDE references.
This causes problems as the FDE does not point to the start of an LSDA chunk.

Use an unnormalized uleb128 for the call-site table length that includes the
padding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 23:34:35 +00:00
..
AsmPrinter LLVM puts padding bytes in the __gcc_except_tab section after the 2010-02-24 23:34:35 +00:00
PBQP Fix various doxygen warnings. 2010-02-22 04:10:52 +00:00
SelectionDAG clean up various VT manipulations, patch by Micah Villmow! PR6337 2010-02-24 22:44:06 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp Always normalize spill weights, also for intervals created by spilling. 2010-02-18 21:33:05 +00:00
CMakeLists.txt Add missed entry to cmake build list file 2010-02-15 22:55:13 +00:00
CodePlacementOpt.cpp Make CodePlacementOpt detect special EH control flow by 2010-02-18 21:25:53 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp
ELFWriter.h
ExactHazardRecognizer.cpp
ExactHazardRecognizer.h
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp
IntrinsicLowering.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp Keep track of phi join registers explicitly in LiveVariables. 2010-02-23 22:43:58 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Keep track of phi join registers explicitly in LiveVariables. 2010-02-23 22:43:58 +00:00
LLVMTargetMachine.cpp Besides removing phi cycles that reduce to a single value, also remove dead 2010-02-13 00:31:44 +00:00
LowerSubregs.cpp
MachineBasicBlock.cpp move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter, 2010-02-17 18:52:56 +00:00
MachineDominators.cpp
MachineFunction.cpp Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254. 2010-02-19 18:17:13 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineInstr.cpp Add non-temporal flags to MachineMemOperand. 2010-02-15 16:48:31 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there 2010-02-15 22:35:59 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
MachineSSAUpdater.cpp
MachineVerifier.cpp
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp
OptimizePHIs.cpp Besides removing phi cycles that reduce to a single value, also remove dead 2010-02-13 00:31:44 +00:00
Passes.cpp Uniformize the way these options are printed. Requested by 2010-02-18 14:37:52 +00:00
PHIElimination.cpp Keep track of phi join registers explicitly in LiveVariables. 2010-02-23 22:43:58 +00:00
PHIElimination.h Dead code elimination 2010-02-23 00:28:53 +00:00
PostRASchedulerList.cpp
PreAllocSplitting.cpp
ProcessImplicitDefs.cpp Fix PR6300. 2010-02-15 22:03:29 +00:00
PrologEpilogInserter.cpp Updated version of r96634 (which was reverted due to failing 176.gcc and 2010-02-22 23:10:38 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocLinearScan.cpp
RegAllocLocal.cpp Reapply 96294; now that I've gotten around to looking 2010-02-16 01:27:47 +00:00
RegAllocPBQP.cpp Remove terminating dot in description. Inconsistency pointed 2010-02-18 14:10:41 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp There are two ways of checking for a given type, for example isa<PointerType>(T) 2010-02-16 11:11:14 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Remember to handle sub-registers when moving imp-defs to a rematted instruction. 2010-02-23 22:44:02 +00:00
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp
SlotIndexes.cpp
Spiller.cpp
Spiller.h
StackProtector.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
StackSlotColoring.cpp
StrongPHIElimination.cpp
TailDuplication.cpp
TargetInstrInfoImpl.cpp
TargetLoweringObjectFileImpl.cpp It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there. 2010-02-21 20:28:15 +00:00
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Uniformize the way these options are printed. Requested by 2010-02-18 14:37:52 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.