mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-03 17:31:50 +00:00
567409db69
This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274189 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
5.0 KiB
C++
127 lines
5.0 KiB
C++
//===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips16 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
|
|
#define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
|
|
|
|
#include "Mips16RegisterInfo.h"
|
|
#include "MipsInstrInfo.h"
|
|
|
|
namespace llvm {
|
|
class MipsSubtarget;
|
|
class Mips16InstrInfo : public MipsInstrInfo {
|
|
const Mips16RegisterInfo RI;
|
|
|
|
public:
|
|
explicit Mips16InstrInfo(const MipsSubtarget &STI);
|
|
|
|
const MipsRegisterInfo &getRegisterInfo() const override;
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than loading from the stack slot.
|
|
unsigned isLoadFromStackSlot(const MachineInstr &MI,
|
|
int &FrameIndex) const override;
|
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than storing to the stack slot.
|
|
unsigned isStoreToStackSlot(const MachineInstr &MI,
|
|
int &FrameIndex) const override;
|
|
|
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const override;
|
|
|
|
void storeRegToStack(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
int64_t Offset) const override;
|
|
|
|
void loadRegFromStack(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
int64_t Offset) const override;
|
|
|
|
bool expandPostRAPseudo(MachineInstr &MI) const override;
|
|
|
|
unsigned getOppositeBranchOpc(unsigned Opc) const override;
|
|
|
|
// Adjust SP by FrameSize bytes. Save RA, S0, S1
|
|
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
// Adjust SP by FrameSize bytes. Restore RA, S0, S1
|
|
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
|
/// Adjust SP by Amount bytes.
|
|
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const override;
|
|
|
|
/// Emit a series of instructions to load an immediate.
|
|
// This is to adjust some FrameReg. We return the new register to be used
|
|
// in place of FrameReg and the adjusted immediate field (&NewImm)
|
|
//
|
|
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator II, const DebugLoc &DL,
|
|
unsigned &NewImm) const;
|
|
|
|
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
|
|
|
|
static bool validSpImm8(int offset) {
|
|
return ((offset & 7) == 0) && isInt<11>(offset);
|
|
}
|
|
|
|
//
|
|
// build the proper one based on the Imm field
|
|
//
|
|
|
|
const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
|
|
|
|
void BuildAddiuSpImm
|
|
(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
|
|
|
|
unsigned getInlineAsmLength(const char *Str,
|
|
const MCAsmInfo &MAI) const override;
|
|
private:
|
|
unsigned getAnalyzableBrOpc(unsigned Opc) const override;
|
|
|
|
void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned Opc) const;
|
|
|
|
// Adjust SP by Amount bytes where bytes can be up to 32bit number.
|
|
void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Reg1, unsigned Reg2) const;
|
|
|
|
// Adjust SP by Amount bytes where bytes can be up to 32bit number.
|
|
void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|