Junmo Park 43a6e3e075 [CodeGenPrepare] Remove load-based heuristic ...

Summary:
Both the hardware and LLVM have changed since 2012.
Now, load-based heuristic don't show big differences any more on OoO cores.

There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5).

Reviewers: spatel, zansari
    
Differential Revision: http://reviews.llvm.org/D16836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261809 91177308-0d34-0410-b5e6-96231b3b80d8

2016-02-25 00:23:27 +00:00

..

AArch64

[CodeGenPrepare] Remove load-based heuristic

2016-02-25 00:23:27 +00:00

AMDGPU

AMDGPU: Add failing testcase for register coalescer

2016-02-22 23:45:42 +00:00

ARM

ARM: sink atomic release barrier as far as possible into cmpxchg.

2016-02-22 20:55:50 +00:00

BPF

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CPP

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Generic

Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86.

2016-02-25 00:12:18 +00:00

Hexagon

[Hexagon] Implement TLS support

2016-02-18 15:42:57 +00:00

Inputs

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Mips

[MC][ELF] Handle MIPS specific .sdata and .sbss directives

2016-02-11 06:45:54 +00:00

MIR

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

MSP430

MSP430InstrInfo::loadRegFromStackSlot forgets to set register def.

2016-02-24 15:15:02 +00:00

NVPTX

Don't tail-duplicate blocks that contain convergent instructions.

2016-02-22 17:50:52 +00:00

PowerPC

Fix for PR26690 take 2

2016-02-22 18:04:00 +00:00

SPARC

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SystemZ

[SystemZ] Fix ABI for i128 argument and return types

2016-02-19 14:10:21 +00:00

Thumb

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Thumb2

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WebAssembly

Revert "[WebAssembly] Stackify code emitted by eliminateFrameIndex"

2016-02-23 22:13:21 +00:00

WinEH

[WinEH] Visit 'unwind to caller' catchswitches nested in catchswitches

2016-02-23 07:18:15 +00:00

X86

[CodeGenPrepare] Remove load-based heuristic

2016-02-25 00:23:27 +00:00

XCore

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