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a941fe247e
This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282143 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.4 KiB
LLVM
37 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr8 \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-P9 --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 -mattr=-power9-vector \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; Function Attrs: nounwind
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define void @test() {
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entry:
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%__a.addr.i = alloca i32, align 4
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%__b.addr.i = alloca <4 x i32>*, align 8
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%i = alloca <4 x i32>, align 16
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%j = alloca <4 x i32>, align 16
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store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16
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store i32 0, i32* %__a.addr.i, align 4
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store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8
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%0 = load i32, i32* %__a.addr.i, align 4
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%1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
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%2 = bitcast <4 x i32>* %1 to i8*
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%3 = getelementptr i8, i8* %2, i32 %0
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%4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
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; CHECK: lwa [[REG0:[0-9]+]],
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; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
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; CHECK: xxswapd [[REG1]], [[REG1]]
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; CHECK-P9: lwa [[REG0:[0-9]+]],
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; CHECK-P9: lxvx [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
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store <4 x i32> %4, <4 x i32>* %j, align 16
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ret void
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}
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; Function Attrs: nounwind readonly
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declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
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