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7ec26d4fef
is defined! The users were checking the proper thing (Defined + PartialDeadDef), but the information may have been wrong for other use cases, so fix that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267641 91177308-0d34-0410-b5e6-96231b3b80d8
344 lines
11 KiB
C++
344 lines
11 KiB
C++
//===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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class UnpackMachineBundles : public MachineFunctionPass {
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public:
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static char ID; // Pass identification
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UnpackMachineBundles(std::function<bool(const Function &)> Ftor = nullptr)
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: MachineFunctionPass(ID), PredicateFtor(Ftor) {
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initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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std::function<bool(const Function &)> PredicateFtor;
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};
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} // end anonymous namespace
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char UnpackMachineBundles::ID = 0;
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char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
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INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
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"Unpack machine instruction bundles", false, false)
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bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
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if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
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return false;
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bool Changed = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
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MIE = MBB->instr_end(); MII != MIE; ) {
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MachineInstr *MI = &*MII;
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// Remove BUNDLE instruction and the InsideBundle flags from bundled
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// instructions.
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if (MI->isBundle()) {
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while (++MII != MIE && MII->isBundledWithPred()) {
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MII->unbundleFromPred();
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for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MII->getOperand(i);
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if (MO.isReg() && MO.isInternalRead())
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MO.setIsInternalRead(false);
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}
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}
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MI->eraseFromParent();
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Changed = true;
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continue;
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}
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++MII;
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}
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}
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return Changed;
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}
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FunctionPass *
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llvm::createUnpackMachineBundles(std::function<bool(const Function &)> Ftor) {
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return new UnpackMachineBundles(Ftor);
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}
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namespace {
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class FinalizeMachineBundles : public MachineFunctionPass {
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public:
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static char ID; // Pass identification
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FinalizeMachineBundles() : MachineFunctionPass(ID) {
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initializeFinalizeMachineBundlesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char FinalizeMachineBundles::ID = 0;
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char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
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INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
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"Finalize machine instruction bundles", false, false)
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bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
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return llvm::finalizeBundles(MF);
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}
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/// finalizeBundle - Finalize a machine instruction bundle which includes
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/// a sequence of instructions starting from FirstMI to LastMI (exclusive).
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/// This routine adds a BUNDLE instruction to represent the bundle, it adds
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/// IsInternalRead markers to MachineOperands which are defined inside the
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/// bundle, and it copies externally visible defs and uses to the BUNDLE
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/// instruction.
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void llvm::finalizeBundle(MachineBasicBlock &MBB,
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MachineBasicBlock::instr_iterator FirstMI,
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MachineBasicBlock::instr_iterator LastMI) {
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assert(FirstMI != LastMI && "Empty bundle?");
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MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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MachineInstrBuilder MIB =
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BuildMI(MF, FirstMI->getDebugLoc(), TII->get(TargetOpcode::BUNDLE));
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Bundle.prepend(MIB);
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SmallVector<unsigned, 32> LocalDefs;
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SmallSet<unsigned, 32> LocalDefSet;
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SmallSet<unsigned, 8> DeadDefSet;
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SmallSet<unsigned, 16> KilledDefSet;
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SmallVector<unsigned, 8> ExternUses;
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SmallSet<unsigned, 8> ExternUseSet;
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SmallSet<unsigned, 8> KilledUseSet;
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SmallSet<unsigned, 8> UndefUseSet;
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SmallVector<MachineOperand*, 4> Defs;
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for (; FirstMI != LastMI; ++FirstMI) {
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for (unsigned i = 0, e = FirstMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = FirstMI->getOperand(i);
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if (!MO.isReg())
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continue;
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if (MO.isDef()) {
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Defs.push_back(&MO);
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continue;
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}
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (LocalDefSet.count(Reg)) {
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MO.setIsInternalRead();
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if (MO.isKill())
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// Internal def is now killed.
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KilledDefSet.insert(Reg);
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} else {
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if (ExternUseSet.insert(Reg).second) {
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ExternUses.push_back(Reg);
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if (MO.isUndef())
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UndefUseSet.insert(Reg);
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}
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if (MO.isKill())
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// External def is now killed.
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KilledUseSet.insert(Reg);
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}
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}
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for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
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MachineOperand &MO = *Defs[i];
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (LocalDefSet.insert(Reg).second) {
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LocalDefs.push_back(Reg);
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if (MO.isDead()) {
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DeadDefSet.insert(Reg);
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}
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} else {
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// Re-defined inside the bundle, it's no longer killed.
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KilledDefSet.erase(Reg);
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if (!MO.isDead())
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// Previously defined but dead.
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DeadDefSet.erase(Reg);
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}
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if (!MO.isDead()) {
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
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unsigned SubReg = *SubRegs;
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if (LocalDefSet.insert(SubReg).second)
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LocalDefs.push_back(SubReg);
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}
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}
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}
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Defs.clear();
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}
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SmallSet<unsigned, 32> Added;
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for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
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unsigned Reg = LocalDefs[i];
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if (Added.insert(Reg).second) {
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// If it's not live beyond end of the bundle, mark it dead.
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bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
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MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
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getImplRegState(true));
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}
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}
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for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
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unsigned Reg = ExternUses[i];
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bool isKill = KilledUseSet.count(Reg);
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bool isUndef = UndefUseSet.count(Reg);
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MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
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getImplRegState(true));
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}
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}
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/// finalizeBundle - Same functionality as the previous finalizeBundle except
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/// the last instruction in the bundle is not provided as an input. This is
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/// used in cases where bundles are pre-determined by marking instructions
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/// with 'InsideBundle' marker. It returns the MBB instruction iterator that
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/// points to the end of the bundle.
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MachineBasicBlock::instr_iterator
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llvm::finalizeBundle(MachineBasicBlock &MBB,
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MachineBasicBlock::instr_iterator FirstMI) {
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MachineBasicBlock::instr_iterator E = MBB.instr_end();
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MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
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while (LastMI != E && LastMI->isInsideBundle())
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++LastMI;
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finalizeBundle(MBB, FirstMI, LastMI);
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return LastMI;
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}
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/// finalizeBundles - Finalize instruction bundles in the specified
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/// MachineFunction. Return true if any bundles are finalized.
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bool llvm::finalizeBundles(MachineFunction &MF) {
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bool Changed = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock &MBB = *I;
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MachineBasicBlock::instr_iterator MII = MBB.instr_begin();
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MachineBasicBlock::instr_iterator MIE = MBB.instr_end();
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if (MII == MIE)
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continue;
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assert(!MII->isInsideBundle() &&
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"First instr cannot be inside bundle before finalization!");
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for (++MII; MII != MIE; ) {
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if (!MII->isInsideBundle())
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++MII;
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else {
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MII = finalizeBundle(MBB, std::prev(MII));
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Changed = true;
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}
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}
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}
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return Changed;
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}
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//===----------------------------------------------------------------------===//
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// MachineOperand iterator
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//===----------------------------------------------------------------------===//
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MachineOperandIteratorBase::VirtRegInfo
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MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg,
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SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {
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VirtRegInfo RI = { false, false, false };
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for(; isValid(); ++*this) {
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MachineOperand &MO = deref();
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if (!MO.isReg() || MO.getReg() != Reg)
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continue;
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// Remember each (MI, OpNo) that refers to Reg.
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if (Ops)
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Ops->push_back(std::make_pair(MO.getParent(), getOperandNo()));
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// Both defs and uses can read virtual registers.
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if (MO.readsReg()) {
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RI.Reads = true;
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if (MO.isDef())
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RI.Tied = true;
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}
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// Only defs can write.
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if (MO.isDef())
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RI.Writes = true;
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else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
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RI.Tied = true;
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}
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return RI;
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}
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MachineOperandIteratorBase::PhysRegInfo
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MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
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const TargetRegisterInfo *TRI) {
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bool AllDefsDead = true;
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PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"analyzePhysReg not given a physical register!");
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for (; isValid(); ++*this) {
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MachineOperand &MO = deref();
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if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
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PRI.Clobbered = true;
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continue;
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}
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
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continue;
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if (!TRI->regsOverlap(MOReg, Reg))
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continue;
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bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
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if (MO.readsReg()) {
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PRI.Read = true;
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if (Covered) {
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PRI.FullyRead = true;
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if (MO.isKill())
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PRI.Killed = true;
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}
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} else if (MO.isDef()) {
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PRI.Defined = true;
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if (Covered)
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PRI.FullyDefined = true;
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if (!MO.isDead())
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AllDefsDead = false;
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}
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}
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if (AllDefsDead) {
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if (PRI.FullyDefined || PRI.Clobbered)
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PRI.DeadDef = true;
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else if (PRI.Defined)
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PRI.PartialDeadDef = true;
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}
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return PRI;
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}
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