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458b5f3d9b
Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
2.2 KiB
LLVM
56 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=1 | FileCheck %s
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel-abort=1 | FileCheck %s
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@sj = global i32 200000, align 4
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@sk = global i32 -47, align 4
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@uj = global i32 200000, align 4
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@uk = global i32 43, align 4
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@si = common global i32 0, align 4
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@ui = common global i32 0, align 4
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define void @divs() {
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; CHECK-LABEL: divs:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: div $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @sj, align 4
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%2 = load i32, i32* @sk, align 4
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%div = sdiv i32 %1, %2
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store i32 %div, i32* @si, align 4
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ret void
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}
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define void @divu() {
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; CHECK-LABEL: divu:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: divu $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @uj, align 4
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%2 = load i32, i32* @uk, align 4
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%div = udiv i32 %1, %2
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store i32 %div, i32* @ui, align 4
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ret void
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}
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