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38d5e1c36d
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
2.4 KiB
LLVM
51 lines
2.4 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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; This shader has the potential to generated illeagal VGPR to SGPR copies if
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; the wrong register class is used for the REG_SEQUENCE instructions.
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; CHECK: @main
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; CHECK: IMAGE_SAMPLE_B VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 15, 0, 0, 0, 0, 0, 0, 0, VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}
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define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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%23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
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%24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
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%25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
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%26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
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%27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
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%28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
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%29 = bitcast float %22 to i32
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%30 = bitcast float %27 to i32
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%31 = bitcast float %28 to i32
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%32 = insertelement <4 x i32> undef, i32 %29, i32 0
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%33 = insertelement <4 x i32> %32, i32 %30, i32 1
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%34 = insertelement <4 x i32> %33, i32 %31, i32 2
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%35 = insertelement <4 x i32> %34, i32 undef, i32 3
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%36 = call <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32> %35, <32 x i8> %24, <16 x i8> %26, i32 2)
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%37 = extractelement <4 x float> %36, i32 0
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%38 = extractelement <4 x float> %36, i32 1
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%39 = extractelement <4 x float> %36, i32 2
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%40 = extractelement <4 x float> %36, i32 3
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %37, float %38, float %39, float %40)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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!0 = metadata !{metadata !"const", null, i32 1}
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