llvm/lib/CodeGen
Bill Wendling 57f0db833d Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-24 08:30:20 +00:00
..
AsmPrinter Overhaul my earlier submission due to feedback. It's a large patch, but most of 2009-02-24 08:30:20 +00:00
SelectionDAG Overhaul my earlier submission due to feedback. It's a large patch, but most of 2009-02-24 08:30:20 +00:00
BranchFolding.cpp Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 2009-02-09 07:14:22 +00:00
CMakeLists.txt Experimental post-pass scheduling support. Post-pass scheduling 2008-11-19 23:18:57 +00:00
DeadMachineInstructionElim.cpp
ELFWriter.cpp Add support to the JIT for true non-lazy operation. When a call to a function 2009-02-18 08:31:02 +00:00
ELFWriter.h
GCMetadata.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Add missing break statements, fixing PR3503. 2009-02-07 22:37:06 +00:00
LatencyPriorityQueue.cpp Add initial support for back-scheduling address computations, 2008-12-16 03:35:01 +00:00
LiveInterval.cpp MergeValueInto is too smart: it might choose to do the merge the opposite direction. 2009-02-02 22:42:01 +00:00
LiveIntervalAnalysis.cpp Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register. 2009-02-08 11:04:35 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 2009-01-20 21:25:12 +00:00
LLVMTargetMachine.cpp Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. 2009-02-09 08:45:39 +00:00
LoopAligner.cpp Avoid inserting noop's in the middle of a loop. 2008-11-27 01:16:00 +00:00
LowerSubregs.cpp Teach LowerSubregs to preserve kill/dead information when lowering 2008-12-18 22:14:08 +00:00
MachineBasicBlock.cpp Delete unnecessary parens around return values. 2009-01-08 22:19:34 +00:00
MachineDominators.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
MachineFunction.cpp Constify and don't return a reference. 2009-02-04 00:05:34 +00:00
MachineInstr.cpp Print out debug info when printing the machine instruction. 2009-02-19 21:44:55 +00:00
MachineLICM.cpp Machine LICM increases register pressure and it almost always increase code size. For now, disable it for optimizing for size. 2009-02-05 08:51:13 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Remove dead code. 2009-02-03 19:46:28 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Move createVirtualRegister out-of-line. 2008-12-08 04:54:11 +00:00
MachineSink.cpp Fix PR3522. It's not safe to sink into landing pad BB's. 2009-02-15 08:36:12 +00:00
MachOWriter.cpp Add support to the JIT for true non-lazy operation. When a call to a function 2009-02-18 08:31:02 +00:00
MachOWriter.h Rename getABITypeSize to getTypePaddedSize, as 2009-01-12 20:38:59 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
OcamlGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
Passes.cpp
PBQP.cpp
PBQP.h
PHIElimination.cpp Explicitly pass in debug location information to BuildMI. 2009-02-03 02:29:34 +00:00
PhysRegTracker.h
PostRASchedulerList.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
PreAllocSplitting.cpp Fix a crash in the pre-alloc splitter exposed by recent codegen changes. 2009-02-20 10:02:23 +00:00
PrologEpilogInserter.cpp Rename getAnalysisToUpdate to getAnalysisIfAvailable. 2009-01-28 13:14:17 +00:00
PseudoSourceValue.cpp Have PseudoSourceValue override Value::dump, so that it works 2008-12-03 21:37:21 +00:00
README.txt
RegAllocBigBlock.cpp Adjust the sizes for a few SmallVectors to reflect their usage. 2009-02-12 17:29:01 +00:00
RegAllocLinearScan.cpp Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
RegAllocLocal.cpp Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins. 2009-01-29 18:37:30 +00:00
RegAllocPBQP.cpp Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
RegAllocSimple.cpp Silience unused warnings. 2008-12-23 21:55:04 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Tidy up #includes, deleting a bunch of unnecessary #includes. 2009-01-05 17:59:02 +00:00
ScheduleDAG.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGEmit.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.h When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGPrinter.cpp Apparently some MachineBasicBlock's don't have corresponding llvm basic blocks. 2009-02-11 23:42:39 +00:00
ShadowStackGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
SimpleRegisterCoalescing.cpp If a use operand is marked isKill, don't forget to add kill to its live interval as well. 2009-02-22 08:35:56 +00:00
SimpleRegisterCoalescing.h ReMaterializeTrivialDef need to trim the live interval to the last kill if the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. 2009-02-05 08:45:04 +00:00
StackProtector.cpp Rename getABITypeSize to getTypePaddedSize, as 2009-01-12 20:38:59 +00:00
StackSlotColoring.cpp Add a debugging option for SSC DCE. 2009-02-24 05:44:18 +00:00
StrongPHIElimination.cpp
TargetInstrInfoImpl.cpp Explicitly pass in debug location information to BuildMI. 2009-02-03 02:29:34 +00:00
TwoAddressInstructionPass.cpp If two-address def is dead and the instruction does not define other registers, and it doesn't produce side effects, just delete the instruction. 2009-02-21 03:14:25 +00:00
UnreachableBlockElim.cpp Rename getAnalysisToUpdate to getAnalysisIfAvailable. 2009-01-28 13:14:17 +00:00
VirtRegMap.cpp A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes. 2009-02-17 06:41:03 +00:00
VirtRegMap.h Tidy up #includes, deleting a bunch of unnecessary #includes. 2009-01-05 17:59:02 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4