llvm/lib/Target/Sparc
Reid Spencer 47857812e2 For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 05:55:36 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
DelaySlotFiller.cpp eliminate static ctors for Statistic objects. 2006-12-19 22:59:26 +00:00
FPMover.cpp eliminate static ctors for Statistic objects. 2006-12-19 22:59:26 +00:00
Makefile don't dist internal readme 2006-10-28 00:51:15 +00:00
README.txt Done 2006-02-09 20:00:19 +00:00
Sparc.h silence warnings 2006-11-03 01:11:05 +00:00
Sparc.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
SparcAsmPrinter.cpp eliminate static ctors for Statistic objects. 2006-12-19 22:59:26 +00:00
SparcInstrFormats.td Use a couple of multiclass patterns to factor some integer ops. 2006-09-01 22:28:02 +00:00
SparcInstrInfo.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
SparcInstrInfo.h implement uncond branch insertion for sparc to fix regressions from last night 2006-10-24 16:39:19 +00:00
SparcInstrInfo.td remove redundant/dead vars 2006-11-03 23:47:20 +00:00
SparcISelDAGToDAG.cpp For PR950: 2006-12-31 05:55:36 +00:00
SparcRegisterInfo.cpp What should be the last unnecessary <iostream>s in the library. 2006-12-07 22:21:48 +00:00
SparcRegisterInfo.h Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
SparcRegisterInfo.td Constify some methods. Patch provided by Anton Vayvod, thanks! 2006-08-17 22:00:08 +00:00
SparcSubtarget.cpp Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
SparcSubtarget.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcTargetAsmInfo.cpp Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetMachine.cpp What should be the last unnecessary <iostream>s in the library. 2006-12-07 22:21:48 +00:00
SparcTargetMachine.h 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots