Zhan Jun Liau 2738e9ca9e [SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities ...

Summary: Add support for the z13 instructions LOCHI and LOCGHI which
conditionally load immediate values.  Add target instruction info hooks so
that if conversion will allow predication of LHI/LGHI.

Author: RolandF

Reviewers: uweigand

Subscribers: zhanjunl

Commiting on behalf of Roland.

Differential Revision: http://reviews.llvm.org/D22117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275086 91177308-0d34-0410-b5e6-96231b3b80d8

2016-07-11 18:45:03 +00:00

..

AArch64

AArch64: TableGenerate system instruction operands.

2016-07-05 21:23:04 +00:00

AMDGPU

[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)

2016-07-08 15:12:46 +00:00

ARM

RAS extensions are part of ARMv8.2-A. This change enables them by introducing a

2016-06-03 14:03:27 +00:00

Hexagon

[Hexagon] Treat all conditional branches as predicted (not-taken by default)

2016-05-09 18:22:07 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support

2016-07-11 07:41:56 +00:00

PowerPC

This reverts commit r265505.

2016-04-28 20:00:42 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities

2016-07-11 18:45:03 +00:00

X86

Add new flag and intrinsic support for MWAITX and MONITORX instructions

2016-05-18 11:59:12 +00:00

XCore

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00