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e3e43d9d57
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
4.2 KiB
C++
114 lines
4.2 KiB
C++
//===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstring>
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using namespace llvm;
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static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> ProcDesc,
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ArrayRef<SubtargetFeatureKV> ProcFeatures) {
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SubtargetFeatures Features(FS);
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return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
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}
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void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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if (!CPU.empty())
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CPUSchedModel = &getSchedModelForCPU(CPU);
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else
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CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
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}
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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}
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MCSubtargetInfo::MCSubtargetInfo(
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const Triple &TT, StringRef C, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
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ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
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ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
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InitMCProcessorInfo(CPU, FS);
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version does not change the implied bits.
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FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
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FeatureBits.flip(FB);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
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FeatureBits ^= FB;
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return FeatureBits;
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version will also change all implied bits.
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FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
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SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
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SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
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assert(ProcSchedModels && "Processor machine model not available!");
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ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
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assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
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[](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
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return strcmp(LHS.Key, RHS.Key) < 0;
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}) &&
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"Processor machine model table is not sorted");
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// Find entry
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auto Found =
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std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
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if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
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if (CPU != "help") // Don't error if the user asked for help.
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errs() << "'" << CPU
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<< "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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return MCSchedModel::GetDefaultSchedModel();
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}
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assert(Found->Value && "Missing processor SchedModel value");
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return *(const MCSchedModel *)Found->Value;
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}
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InstrItineraryData
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MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
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return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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}
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/// Initialize an InstrItineraryData instance.
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void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
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InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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ForwardingPaths);
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}
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