llvm/test/CodeGen/ARM/ldstrex-m.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

60 lines
1.1 KiB
LLVM

; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s
; CHECK-LABEL: f0:
; CHECK-NOT: ldrexd
define i64 @f0(i64* %p) nounwind readonly {
entry:
%0 = load atomic i64, i64* %p seq_cst, align 8
ret i64 %0
}
; CHECK-LABEL: f1:
; CHECK-NOT: strexd
define void @f1(i64* %p) nounwind readonly {
entry:
store atomic i64 0, i64* %p seq_cst, align 8
ret void
}
; CHECK-LABEL: f2:
; CHECK-NOT: ldrexd
; CHECK-NOT: strexd
define i64 @f2(i64* %p) nounwind readonly {
entry:
%0 = atomicrmw add i64* %p, i64 1 seq_cst
ret i64 %0
}
; CHECK-LABEL: f3:
; CHECK: ldr
define i32 @f3(i32* %p) nounwind readonly {
entry:
%0 = load atomic i32, i32* %p seq_cst, align 4
ret i32 %0
}
; CHECK-LABEL: f4:
; CHECK: ldrb
define i8 @f4(i8* %p) nounwind readonly {
entry:
%0 = load atomic i8, i8* %p seq_cst, align 4
ret i8 %0
}
; CHECK-LABEL: f5:
; CHECK: str
define void @f5(i32* %p) nounwind readonly {
entry:
store atomic i32 0, i32* %p seq_cst, align 4
ret void
}
; CHECK-LABEL: f6:
; CHECK: ldrex
; CHECK: strex
define i32 @f6(i32* %p) nounwind readonly {
entry:
%0 = atomicrmw add i32* %p, i32 1 seq_cst
ret i32 %0
}