Daniel Sanders ed541fe200 [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. ... Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8		2015-10-15 14:34:23 +00:00
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AArch64	MIR Serialization: Use the global value syntax for global value memory operands.	2015-08-20 00:20:03 +00:00
AMDGPU	MIR Serialization: Change MIR syntax - use custom syntax for MBBs.	2015-08-13 23:10:16 +00:00
ARM	MIR Serialization: Serialize the '.cfi_same_value' CFI directive.	2015-08-14 21:55:58 +00:00
Generic	MIR Serialization: Change MIR syntax - use custom syntax for MBBs.	2015-08-13 23:10:16 +00:00
Mips	[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.	2015-10-15 14:34:23 +00:00
NVPTX	MIR Serialization: Change MIR syntax - use custom syntax for MBBs.	2015-08-13 23:10:16 +00:00
PowerPC	Fix PR 24724 - The implicit register verifier shouldn't assume certain operand	2015-09-10 14:04:34 +00:00
X86	Fix PR 24724 - The implicit register verifier shouldn't assume certain operand	2015-09-10 14:04:34 +00:00
lit.local.cfg	Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).	2015-05-27 18:02:19 +00:00