Chris Dewhurst 9343ace500 This change adds co-processor condition branching and conditional traps to the Sparc back-end. ... This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263044 91177308-0d34-0410-b5e6-96231b3b80d8		2016-03-09 18:20:21 +00:00
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lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
sparc-fp.txt	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
sparc-mem.txt	[Sparc] Implement i64 load/store support for 32-bit sparc.	2015-08-10 19:11:39 +00:00
sparc-special-registers.txt	The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.	2016-02-27 12:49:59 +00:00
sparc-v9.txt	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
sparc.txt	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00