mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-03 17:31:50 +00:00
245caec9b3
_foo:
smull r0, r1, r1, r0
smull r2, r3, r3, r2
adds r0, r2, r0
adc r1, r3, r1
bx lr
to
_foo:
smull r0, r1, r1, r0
smlal r0, r1, r3, r2
bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226904 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
3.6 KiB
LLVM
119 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
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; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE
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; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
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; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE
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; Check generated signed and unsigned multiply accumulate long.
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define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
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;CHECK-LABEL: MACLongTest1:
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;CHECK: umlal
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%conv = zext i32 %a to i64
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%conv1 = zext i32 %b to i64
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%mul = mul i64 %conv1, %conv
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%add = add i64 %mul, %c
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ret i64 %add
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}
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define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
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;CHECK-LABEL: MACLongTest2:
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;CHECK: smlal
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%conv = sext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%mul = mul nsw i64 %conv1, %conv
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%add = add nsw i64 %mul, %c
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ret i64 %add
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}
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define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
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;CHECK-LABEL: MACLongTest3:
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;CHECK: umlal
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%conv = zext i32 %b to i64
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%conv1 = zext i32 %a to i64
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%mul = mul i64 %conv, %conv1
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%conv2 = zext i32 %c to i64
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%add = add i64 %mul, %conv2
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ret i64 %add
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}
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define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
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;CHECK-LABEL: MACLongTest4:
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;CHECK: smlal
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%conv = sext i32 %b to i64
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%conv1 = sext i32 %a to i64
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%mul = mul nsw i64 %conv, %conv1
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%conv2 = sext i32 %c to i64
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%add = add nsw i64 %mul, %conv2
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ret i64 %add
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}
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; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.
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; + Without @earlyclobber the v7 code is natural. With it, the first two
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; registers must be distinct from the third.
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; + Without "$Rd = $R", this can be satisfied without a mov before the umlal
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; by trying to use 6 different registers in the MachineInstr. The natural
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; evolution of this attempt currently leaves only two movs in the final
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; function, both after the umlal. With it, *some* move has to happen
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; before the umlal.
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define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) {
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; CHECK-V7-LE-LABEL: MACLongTest5:
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; CHECK-V7-LE-LABEL: umlal r0, r1, r0, r0
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; CHECK-V7-BE-LABEL: MACLongTest5:
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; CHECK-V7-BE-LABEL: umlal r1, r0, r1, r1
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; CHECK-LABEL: MACLongTest5:
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; CHECK-LE: mov [[RDLO:r[0-9]+]], r0
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; CHECK-LE: umlal [[RDLO]], r1, r0, r0
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; CHECK-LE: mov r0, [[RDLO]]
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; CHECK-BE: mov [[RDLO:r[0-9]+]], r1
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; CHECK-BE: umlal [[RDLO]], r0, r1, r1
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; CHECK-BE: mov r1, [[RDLO]]
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%conv.trunc = trunc i64 %c to i32
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%conv = zext i32 %conv.trunc to i64
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%conv1 = zext i32 %b to i64
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%mul = mul i64 %conv, %conv
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%add = add i64 %mul, %c
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ret i64 %add
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}
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define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
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;CHECK-LABEL: MACLongTest6:
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;CHECK: smull r12, lr, r1, r0
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;CHECK: smlal r12, lr, r3, r2
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%conv = sext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%mul = mul nsw i64 %conv1, %conv
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%conv2 = sext i32 %c to i64
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%conv3 = sext i32 %d to i64
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%mul4 = mul nsw i64 %conv3, %conv2
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%add = add nsw i64 %mul4, %mul
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ret i64 %add
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}
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define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) {
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;CHECK-LABEL: MACLongTest7:
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;CHECK-NOT: smlal
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%conv = sext i32 %lhs to i64
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%conv1 = sext i32 %rhs to i64
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%mul = mul nsw i64 %conv1, %conv
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%shl = shl i64 %mul, 32
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%shr = lshr i64 %mul, 32
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%or = or i64 %shl, %shr
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%add = add i64 %or, %acc
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ret i64 %add
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}
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define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {
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;CHECK-LABEL: MACLongTest8:
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;CHECK-NOT: smlal
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%conv = zext i32 %lhs to i64
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%conv1 = zext i32 %rhs to i64
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%mul = mul nuw i64 %conv1, %conv
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%and = and i64 %mul, 4294967295
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%shl = shl i64 %mul, 32
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%or = or i64 %and, %shl
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%add = add i64 %or, %acc
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ret i64 %add
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}
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