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cf18232c49
Differential Revision: http://reviews.llvm.org/D18769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265482 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
4.3 KiB
LLVM
134 lines
4.3 KiB
LLVM
; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s
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; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s
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; Test how llvm handles return type of {i16, i8}. The return value will be
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; passed in %r0 and %r1.
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; CHECK-LABEL: test:
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; CHECK: bl {{.*}}gen
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; CHECK: sxth {{.*}}, r0
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; CHECK: sxtab r0, {{.*}}, r1
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; CHECK-O0-LABEL: test:
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; CHECK-O0: bl {{.*}}gen
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; CHECK-O0: sxth r0, r0
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; CHECK-O0: sxtb r1, r1
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; CHECK-O0: add r0, r0, r1
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define i16 @test(i32 %key) {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i16, i8 } @gen(i32 %0)
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%v3 = extractvalue { i16, i8 } %call, 0
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%v1 = sext i16 %v3 to i32
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%v5 = extractvalue { i16, i8 } %call, 1
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%v2 = sext i8 %v5 to i32
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%add = add nsw i32 %v1, %v2
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%conv = trunc i32 %add to i16
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ret i16 %conv
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}
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declare swiftcc { i16, i8 } @gen(i32)
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; We can't pass every return value in register, instead, pass everything in
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; memroy.
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; The caller provides space for the return value and passes the address in %r0.
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; The first input argument will be in %r1.
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; CHECK-LABEL: test2:
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; CHECK: mov r1, r0
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; CHECK: mov r0, sp
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; CHECK: bl {{.*}}gen2
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; CHECK-DAG: add
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; CHECK-DAG: ldr {{.*}}, [sp, #16]
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; CHECK-DAG: add
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; CHECK-DAG: add
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; CHECK-DAG: add
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; CHECK-O0-LABEL: test2:
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; CHECK-O0: str r0
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; CHECK-O0: mov r0, sp
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; CHECK-O0: bl {{.*}}gen2
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; CHECK-O0-DAG: ldr {{.*}}, [sp]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #4]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #8]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #12]
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; CHECK-O0-DAG: ldr {{.*}}, [sp, #16]
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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; CHECK-O0-DAG: add
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define i32 @test2(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3
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%v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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%add3 = add nsw i32 %add2, %v8
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ret i32 %add3
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}
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; The address of the return value is passed in %r0.
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; CHECK-LABEL: gen2:
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; CHECK-DAG: str r1, [r0]
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; CHECK-DAG: str r1, [r0, #4]
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; CHECK-DAG: str r1, [r0, #8]
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; CHECK-DAG: str r1, [r0, #12]
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; CHECK-DAG: str r1, [r0, #16]
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; CHECK-O0-LABEL: gen2:
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; CHECK-O0-DAG: str r1, [r0]
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; CHECK-O0-DAG: str r1, [r0, #4]
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; CHECK-O0-DAG: str r1, [r0, #8]
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; CHECK-O0-DAG: str r1, [r0, #12]
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; CHECK-O0-DAG: str r1, [r0, #16]
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define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {
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%Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0
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%Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1
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%Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2
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%Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3
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%Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4
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ret { i32, i32, i32, i32, i32 } %Z4
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}
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; The return value {i32, i32, i32, i32} will be returned via registers %r0, %r1,
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; %r2, %r3.
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; CHECK-LABEL: test3:
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; CHECK: bl {{.*}}gen3
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; CHECK: add r0, r0, r1
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; CHECK: add r0, r0, r2
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; CHECK: add r0, r0, r3
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; CHECK-O0-LABEL: test3:
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; CHECK-O0: bl {{.*}}gen3
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; CHECK-O0: add r0, r0, r1
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; CHECK-O0: add r0, r0, r2
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; CHECK-O0: add r0, r0, r3
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define i32 @test3(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32 } %call, 3
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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ret i32 %add2
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}
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declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
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