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5d9b109181
The current register allocators all use the inline spiller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144477 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
3.0 KiB
LLVM
86 lines
3.0 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -spiller=trivial
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; RUN: llc < %s -verify-machineinstrs -spiller=inline
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; PR8612
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;
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; This test has an inline asm with early-clobber arguments.
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; It is big enough that one of the early clobber registers is spilled.
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;
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; All the spillers would get the live ranges wrong when spilling an early
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; clobber, allowing the undef register to be allocated to the same register as
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; the early clobber.
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;
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
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target triple = "armv7-eabi"
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%0 = type { i32, i32 }
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define void @foo(i32* %in) nounwind {
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entry:
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br label %bb.i
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bb.i: ; preds = %bb.i, %entry
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br i1 undef, label %bb10.preheader.i, label %bb.i
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bb10.preheader.i: ; preds = %bb.i
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br label %bb10.i
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bb10.i: ; preds = %bb10.i, %bb10.preheader.i
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br i1 undef, label %bb27.i, label %bb10.i
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bb27.i: ; preds = %bb10.i
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br label %bb28.i
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bb28.i: ; preds = %bb28.i, %bb27.i
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br i1 undef, label %presymmetry.exit, label %bb28.i
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presymmetry.exit: ; preds = %bb28.i
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%tmp175387 = or i32 undef, 12
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%scevgep101.i = getelementptr i32* %in, i32 undef
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%tmp189401 = or i32 undef, 7
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%scevgep97.i = getelementptr i32* %in, i32 undef
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%tmp198410 = or i32 undef, 1
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%scevgep.i48 = getelementptr i32* %in, i32 undef
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%0 = load i32* %scevgep.i48, align 4
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%1 = add nsw i32 %0, 0
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store i32 %1, i32* undef, align 4
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%asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind
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%asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1
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%2 = shl i32 %asmresult1.i.i34.i.i.i, 1
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%3 = load i32* null, align 4
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%4 = load i32* undef, align 4
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%5 = sub nsw i32 %3, %4
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%6 = load i32* undef, align 4
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%7 = load i32* null, align 4
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%8 = sub nsw i32 %6, %7
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%9 = load i32* %scevgep97.i, align 4
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%10 = load i32* undef, align 4
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%11 = sub nsw i32 %9, %10
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%12 = load i32* null, align 4
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%13 = load i32* %scevgep101.i, align 4
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%14 = sub nsw i32 %12, %13
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%15 = load i32* %scevgep.i48, align 4
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%16 = load i32* null, align 4
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%17 = add nsw i32 %16, %15
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%18 = sub nsw i32 %15, %16
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%19 = load i32* undef, align 4
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%20 = add nsw i32 %19, %2
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%21 = sub nsw i32 %19, %2
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%22 = add nsw i32 %14, %5
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%23 = sub nsw i32 %5, %14
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%24 = add nsw i32 %11, %8
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%25 = sub nsw i32 %8, %11
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%26 = add nsw i32 %21, %23
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store i32 %26, i32* %scevgep.i48, align 4
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%27 = sub nsw i32 %25, %18
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store i32 %27, i32* null, align 4
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%28 = sub nsw i32 %23, %21
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store i32 %28, i32* undef, align 4
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%29 = add nsw i32 %18, %25
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store i32 %29, i32* undef, align 4
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%30 = add nsw i32 %17, %22
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store i32 %30, i32* %scevgep101.i, align 4
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%31 = add nsw i32 %20, %24
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store i32 %31, i32* null, align 4
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unreachable
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}
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