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098c6a547f
Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
4.5 KiB
LLVM
225 lines
4.5 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
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; rdar://8662825
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM: t1:
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; ARM: suble r1, r1, #-2147483647
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; ARM: mov r0, r1
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; T2: t1:
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; T2: mvn r0, #-2147483648
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; T2: addle r1, r0
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; T2: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM: t2:
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; ARM: suble r1, r1, #10
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; ARM: mov r0, r1
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; T2: t2:
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; T2: suble r1, #10
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; T2: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM: t3:
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; ARM: andge r3, r3, r2
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; ARM: mov r0, r3
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; T2: t3:
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; T2: andge r3, r2
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; T2: mov r0, r3
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 -1, i32 %x
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%s = and i32 %z, %y
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ret i32 %s
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}
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define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM: t4:
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; ARM: orrge r3, r3, r2
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; ARM: mov r0, r3
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; T2: t4:
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; T2: orrge r3, r2
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; T2: mov r0, r3
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 0, i32 %x
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%s = or i32 %z, %y
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ret i32 %s
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}
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define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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; ARM: t5:
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; ARM-NOT: moveq
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; ARM: orreq r2, r2, #1
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; T2: t5:
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; T2-NOT: moveq
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; T2: orreq r2, r2, #1
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%tmp1 = icmp eq i32 %a, %b
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%tmp2 = zext i1 %tmp1 to i32
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%tmp3 = or i32 %tmp2, %c
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ret i32 %tmp3
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}
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define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM: t6:
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; ARM-NOT: movge
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; ARM: eorlt r3, r3, r2
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; T2: t6:
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; T2-NOT: movge
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; T2: eorlt r3, r2
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %c, i32 0
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%tmp2 = xor i32 %tmp1, %d
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ret i32 %tmp2
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}
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define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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; ARM: t7:
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; ARM-NOT: lsleq
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; ARM: andeq r2, r2, r2, lsl #1
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; T2: t7:
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; T2-NOT: lsleq.w
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; T2: andeq.w r2, r2, r2, lsl #1
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%tmp1 = shl i32 %c, 1
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%cond = icmp eq i32 %a, %b
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%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
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%tmp3 = and i32 %c, %tmp2
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ret i32 %tmp3
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}
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; Fold ORRri into movcc.
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define i32 @t8(i32 %a, i32 %b) nounwind {
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; ARM: t8:
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; ARM: cmp r0, r1
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; ARM: orrge r0, r1, #1
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; T2: t8:
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; T2: cmp r0, r1
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; T2: orrge r0, r1, #1
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ANDrr into movcc.
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define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM: t9:
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; ARM: cmp r0, r1
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; ARM: andge r0, r1, r2
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; T2: t9:
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; T2: cmp r0, r1
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; T2: andge.w r0, r1, r2
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%x = and i32 %b, %c
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold EORrs into movcc.
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define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM: t10:
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; ARM: cmp r0, r1
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; ARM: eorge r0, r1, r2, lsl #7
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; T2: t10:
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; T2: cmp r0, r1
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; T2: eorge.w r0, r1, r2, lsl #7
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%s = shl i32 %c, 7
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%x = xor i32 %b, %s
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ORRri into movcc, reversing the condition.
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define i32 @t11(i32 %a, i32 %b) nounwind {
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; ARM: t11:
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; ARM: cmp r0, r1
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; ARM: orrlt r0, r1, #1
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; T2: t11:
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; T2: cmp r0, r1
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; T2: orrlt r0, r1, #1
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %x, i32 %a
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ret i32 %tmp1
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}
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; Fold ADDri12 into movcc
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define i32 @t12(i32 %a, i32 %b) nounwind {
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; ARM: t12:
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; ARM: cmp r0, r1
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; ARM: addge r0, r1,
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; T2: t12:
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; T2: cmp r0, r1
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; T2: addwge r0, r1, #3000
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%x = add i32 %b, 3000
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Handle frame index operands.
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define void @pr13628() nounwind uwtable align 2 {
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%x3 = alloca i8, i32 256, align 8
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%x4 = load i8* undef, align 1
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%x5 = icmp ne i8 %x4, 0
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%x6 = select i1 %x5, i8* %x3, i8* null
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call void @bar(i8* %x6) nounwind
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ret void
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}
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declare void @bar(i8*)
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; Fold zext i1 into predicated add
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define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t13
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; ARM: cmp r1, #10
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; ARM: addgt r0, r0, #1
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; T2: t13
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; T2: cmp r1, #10
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; T2: addgt r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = zext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Fold sext i1 into predicated sub
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define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t14
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; ARM: cmp r1, #10
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; ARM: subgt r0, r0, #1
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; T2: t14
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; T2: cmp r1, #10
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; T2: subgt r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = sext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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