Simon Pilgrim 4f38f405fc [X86][SSE] Add vector test for (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) detailed in D19325 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289035 91177308-0d34-0410-b5e6-96231b3b80d8		2016-12-08 10:17:25 +00:00
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AArch64	The few days mentioned in r267095 are over	2016-12-08 00:16:42 +00:00
AMDGPU	AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.	2016-12-07 02:42:15 +00:00
ARM	Summary: Currently there is no way to disable deprecated warning from asm like this	2016-12-05 23:55:13 +00:00
AVR	[AVR] Add MIR tests for a few pseudo instructions	2016-12-08 08:54:41 +00:00
BPF
Generic
Hexagon
Inputs
Lanai	[lanai] Custom lowering of SHL_PARTS	2016-12-02 22:01:28 +00:00
Mips
MIR	AMDGPU: Refactor exp instructions	2016-12-05 20:23:10 +00:00
MSP430	[CodeGen] Fix result type for SMULO/UMULO legalization	2016-12-06 22:49:36 +00:00
NVPTX
PowerPC	[PowerPC] Improvements for BUILD_VECTOR Vol. 4	2016-12-06 11:47:14 +00:00
SPARC
SystemZ	[SystemZ] Support floating-point control register instructions	2016-12-02 18:21:53 +00:00
Thumb
Thumb2
WebAssembly
WinEH
X86	[X86][SSE] Add vector test for (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) detailed in D19325	2016-12-08 10:17:25 +00:00
XCore