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These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
383 lines
13 KiB
C++
383 lines
13 KiB
C++
//===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Alpha implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaInstrInfo.h"
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#include "AlphaMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_CTOR
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#include "AlphaGenInstrInfo.inc"
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using namespace llvm;
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AlphaInstrInfo::AlphaInstrInfo()
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: AlphaGenInstrInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
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RI(*this) {
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}
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unsigned
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AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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case Alpha::LDL:
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case Alpha::LDQ:
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case Alpha::LDBU:
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case Alpha::LDWU:
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case Alpha::LDS:
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case Alpha::LDT:
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if (MI->getOperand(1).isFI()) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned
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AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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case Alpha::STL:
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case Alpha::STQ:
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case Alpha::STB:
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case Alpha::STW:
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case Alpha::STS:
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case Alpha::STT:
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if (MI->getOperand(1).isFI()) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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static bool isAlphaIntCondCode(unsigned Opcode) {
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switch (Opcode) {
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case Alpha::BEQ:
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case Alpha::BNE:
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case Alpha::BGE:
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case Alpha::BGT:
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case Alpha::BLE:
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case Alpha::BLT:
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case Alpha::BLBC:
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case Alpha::BLBS:
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return true;
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default:
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return false;
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}
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}
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unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Alpha branch conditions have two components!");
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
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else // Conditional branch
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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return 1;
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}
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// Two-way Conditional Branch.
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
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return 2;
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}
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void AlphaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
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.addReg(SrcReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
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.addReg(SrcReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
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.addReg(SrcReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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llvm_unreachable("Attempt to copy register that is not GPR or FPR");
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}
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}
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void
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AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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//cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
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// << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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if (RC == Alpha::F4RCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::STS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::F8RCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::STT))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::GPRCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::STQ))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else
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llvm_unreachable("Unhandled register class");
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}
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void
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AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
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// << FrameIdx << "\n";
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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if (RC == Alpha::F4RCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::F8RCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::GPRCRegisterClass)
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BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else
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llvm_unreachable("Unhandled register class");
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}
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static unsigned AlphaRevCondCode(unsigned Opcode) {
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switch (Opcode) {
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case Alpha::BEQ: return Alpha::BNE;
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case Alpha::BNE: return Alpha::BEQ;
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case Alpha::BGE: return Alpha::BLT;
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case Alpha::BGT: return Alpha::BLE;
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case Alpha::BLE: return Alpha::BGT;
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case Alpha::BLT: return Alpha::BGE;
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case Alpha::BLBC: return Alpha::BLBS;
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case Alpha::BLBS: return Alpha::BLBC;
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case Alpha::FBEQ: return Alpha::FBNE;
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case Alpha::FBNE: return Alpha::FBEQ;
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case Alpha::FBGE: return Alpha::FBLT;
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case Alpha::FBGT: return Alpha::FBLE;
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case Alpha::FBLE: return Alpha::FBGT;
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case Alpha::FBLT: return Alpha::FBGE;
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default:
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llvm_unreachable("Unknown opcode");
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}
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return 0; // Not reached
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}
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// Branch analysis.
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bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastInst->getOpcode() == Alpha::BR) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
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LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(2).getMBB();
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Cond.push_back(LastInst->getOperand(0));
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Cond.push_back(LastInst->getOperand(1));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
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if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
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SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
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LastInst->getOpcode() == Alpha::BR) {
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TBB = SecondLastInst->getOperand(2).getMBB();
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Cond.push_back(SecondLastInst->getOperand(0));
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two Alpha::BRs, handle it. The second one is not
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// executed, so remove it.
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if (SecondLastInst->getOpcode() == Alpha::BR &&
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LastInst->getOpcode() == Alpha::BR) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (I->getOpcode() != Alpha::BR &&
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I->getOpcode() != Alpha::COND_BRANCH_I &&
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I->getOpcode() != Alpha::COND_BRANCH_F)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (I->getOpcode() != Alpha::COND_BRANCH_I &&
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I->getOpcode() != Alpha::COND_BRANCH_F)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
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.addReg(Alpha::R31)
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.addReg(Alpha::R31);
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}
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bool AlphaInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
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Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
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return false;
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
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unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
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BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
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GlobalBaseReg).addReg(Alpha::R29);
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RegInfo.addLiveIn(Alpha::R29);
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AlphaFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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/// getGlobalRetAddr - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
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AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
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unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
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if (GlobalRetAddr != 0)
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return GlobalRetAddr;
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// Insert the set of GlobalRetAddr into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
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BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
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GlobalRetAddr).addReg(Alpha::R26);
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RegInfo.addLiveIn(Alpha::R26);
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AlphaFI->setGlobalRetAddr(GlobalRetAddr);
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return GlobalRetAddr;
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}
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