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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.2 KiB
C++
129 lines
4.2 KiB
C++
//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the XCore Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
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#include "XCoreRegisterInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// XCoreDisassembler - a disasembler class for XCore.
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class XCoreDisassembler : public MCDisassembler {
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const MCRegisterInfo *RegInfo;
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public:
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/// Constructor - Initializes the disassembler.
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///
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XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
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MCDisassembler(STI), RegInfo(Info) {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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const MCRegisterInfo *getRegInfo() const { return RegInfo; }
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};
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}
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static bool readInstruction16(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint16_t &insn) {
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uint8_t Bytes[4];
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// We want to read exactly 2 Bytes of data.
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if (region.readBytes(address, 2, Bytes, NULL) == -1) {
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size = 0;
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return false;
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}
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// Encoded as a little-endian 16-bit word in the stream.
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insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return true;
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}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
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return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
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}
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo > 11)
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return MCDisassembler::Fail;
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unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint16_t low;
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if (!readInstruction16(Region, Address, Size, low)) {
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return Fail;
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}
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// Calling the auto-generated decoder function.
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DecodeStatus Result = decodeInstruction(DecoderTable16, instr, low, Address,
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this, STI);
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if (Result != Fail) {
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Size = 2;
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return Result;
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}
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return Fail;
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}
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namespace llvm {
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extern Target TheXCoreTarget;
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}
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static MCDisassembler *createXCoreDisassembler(const Target &T,
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const MCSubtargetInfo &STI) {
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return new XCoreDisassembler(STI, T.createMCRegInfo(""));
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}
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extern "C" void LLVMInitializeXCoreDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
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createXCoreDisassembler);
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}
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