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a3b03dccc4
Summary: Add getMemOpBaseRegImmOfsWidth to enable determining independence during MiSched. Reviewers: eliben, majnemer Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18903 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266338 91177308-0d34-0410-b5e6-96231b3b80d8
415 lines
14 KiB
C++
415 lines
14 KiB
C++
//===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Lanai implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Lanai.h"
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#include "LanaiInstrInfo.h"
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#include "LanaiMachineFunctionInfo.h"
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#include "LanaiTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "LanaiGenInstrInfo.inc"
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LanaiInstrInfo::LanaiInstrInfo()
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: LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
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RegisterInfo() {}
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void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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DebugLoc DL, unsigned DestinationRegister,
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unsigned SourceRegister,
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bool KillSource) const {
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if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
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.addReg(SourceRegister, getKillRegState(KillSource))
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.addImm(0);
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}
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void LanaiInstrInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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unsigned SourceRegister, bool IsKill, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const {
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DebugLoc DL;
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if (Position != MBB.end()) {
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DL = Position->getDebugLoc();
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}
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if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
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llvm_unreachable("Can't store this register to stack slot");
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}
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BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
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.addReg(SourceRegister, getKillRegState(IsKill))
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addImm(LPAC::ADD);
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}
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void LanaiInstrInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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unsigned DestinationRegister, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const {
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DebugLoc DL;
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if (Position != MBB.end()) {
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DL = Position->getDebugLoc();
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}
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if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
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llvm_unreachable("Can't load this register from stack slot");
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}
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BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addImm(LPAC::ADD);
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}
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bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
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MachineInstr *MIb,
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AliasAnalysis *AA) const {
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assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store.");
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assert(MIb && MIb->mayLoadOrStore() && "MIb must be a load or store.");
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if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
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MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
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return false;
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// Retrieve the base register, offset from the base register and width. Width
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// is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
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// base registers are identical, and the offset of a lower memory access +
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// the width doesn't overlap the offset of a higher memory access,
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// then the memory accesses are different.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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unsigned BaseRegA = 0, BaseRegB = 0;
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int64_t OffsetA = 0, OffsetB = 0;
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unsigned int WidthA = 0, WidthB = 0;
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if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) &&
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getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
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if (BaseRegA == BaseRegB) {
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int LowOffset = std::min(OffsetA, OffsetB);
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int HighOffset = std::max(OffsetA, OffsetB);
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int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
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if (LowOffset + LowWidth <= HighOffset)
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return true;
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}
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}
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return false;
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}
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bool LanaiInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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return false;
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}
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static LPCC::CondCode GetOppositeBranchCondition(LPCC::CondCode CC) {
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switch (CC) {
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case LPCC::ICC_T: // true
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return LPCC::ICC_F;
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case LPCC::ICC_F: // false
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return LPCC::ICC_T;
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case LPCC::ICC_HI: // high
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return LPCC::ICC_LS;
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case LPCC::ICC_LS: // low or same
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return LPCC::ICC_HI;
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case LPCC::ICC_CC: // carry cleared
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return LPCC::ICC_CS;
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case LPCC::ICC_CS: // carry set
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return LPCC::ICC_CC;
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case LPCC::ICC_NE: // not equal
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return LPCC::ICC_EQ;
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case LPCC::ICC_EQ: // equal
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return LPCC::ICC_NE;
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case LPCC::ICC_VC: // oVerflow cleared
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return LPCC::ICC_VS;
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case LPCC::ICC_VS: // oVerflow set
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return LPCC::ICC_VC;
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case LPCC::ICC_PL: // plus (note: 0 is "minus" too here)
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return LPCC::ICC_MI;
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case LPCC::ICC_MI: // minus
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return LPCC::ICC_PL;
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case LPCC::ICC_GE: // greater than or equal
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return LPCC::ICC_LT;
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case LPCC::ICC_LT: // less than
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return LPCC::ICC_GE;
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case LPCC::ICC_GT: // greater than
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return LPCC::ICC_LE;
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case LPCC::ICC_LE: // less than or equal
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return LPCC::ICC_GT;
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default:
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llvm_unreachable("Invalid condtional code");
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}
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}
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// The AnalyzeBranch function is used to examine conditional instructions and
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// remove unnecessary instructions. This method is used by BranchFolder and
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// IfConverter machine function passes to improve the CFG.
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// - TrueBlock is set to the destination if condition evaluates true (it is the
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// nullptr if the destination is the fall-through branch);
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// - FalseBlock is set to the destination if condition evaluates to false (it
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// is the nullptr if the branch is unconditional);
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// - condition is populated with machine operands needed to generate the branch
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// to insert in InsertBranch;
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// Returns: false if branch could successfully be analyzed.
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bool LanaiInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TrueBlock,
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MachineBasicBlock *&FalseBlock,
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SmallVectorImpl<MachineOperand> &Condition,
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bool AllowModify) const {
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// Iterator to current instruction being considered.
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MachineBasicBlock::iterator Instruction = MBB.end();
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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while (Instruction != MBB.begin()) {
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--Instruction;
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// Skip over debug values.
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if (Instruction->isDebugValue())
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continue;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(*Instruction))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!Instruction->isBranch())
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return true;
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// Handle unconditional branches.
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if (Instruction->getOpcode() == Lanai::BT) {
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if (!AllowModify) {
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TrueBlock = Instruction->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a branch, delete them.
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while (std::next(Instruction) != MBB.end()) {
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std::next(Instruction)->eraseFromParent();
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}
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Condition.clear();
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FalseBlock = nullptr;
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// Delete the jump if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
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TrueBlock = nullptr;
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Instruction->eraseFromParent();
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Instruction = MBB.end();
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continue;
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}
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// TrueBlock is used to indicate the unconditional destination.
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TrueBlock = Instruction->getOperand(0).getMBB();
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continue;
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}
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// Handle conditional branches
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unsigned Opcode = Instruction->getOpcode();
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if (Opcode != Lanai::BRCC)
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return true; // Unknown opcode.
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// Multiple conditional branches are not handled here so only proceed if
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// there are no conditions enqueued.
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if (Condition.empty()) {
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LPCC::CondCode BranchCond =
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static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
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// TrueBlock is the target of the previously seen unconditional branch.
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FalseBlock = TrueBlock;
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TrueBlock = Instruction->getOperand(0).getMBB();
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Condition.push_back(MachineOperand::CreateImm(BranchCond));
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continue;
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}
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// Multiple conditional branches are not handled.
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return true;
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}
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// Return false indicating branch successfully analyzed.
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return false;
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}
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// ReverseBranchCondition - Reverses the branch condition of the specified
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// condition list, returning false on success and true if it cannot be
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// reversed.
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bool LanaiInstrInfo::ReverseBranchCondition(
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SmallVectorImpl<llvm::MachineOperand> &Condition) const {
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assert((Condition.size() == 1) &&
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"Lanai branch conditions should have one component.");
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LPCC::CondCode BranchCond =
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static_cast<LPCC::CondCode>(Condition[0].getImm());
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Condition[0].setImm(GetOppositeBranchCondition(BranchCond));
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return false;
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}
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// Insert the branch with condition specified in condition and given targets
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// (TrueBlock and FalseBlock). This function returns the number of machine
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// instructions inserted.
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unsigned LanaiInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TrueBlock,
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MachineBasicBlock *FalseBlock,
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ArrayRef<MachineOperand> Condition,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TrueBlock && "InsertBranch must not be told to insert a fallthrough");
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// If condition is empty then an unconditional branch is being inserted.
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if (Condition.empty()) {
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assert(!FalseBlock && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
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return 1;
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}
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// Else a conditional branch is inserted.
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assert((Condition.size() == 1) &&
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"Lanai branch conditions should have one component.");
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unsigned ConditionalCode = Condition[0].getImm();
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BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
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// If no false block, then false behavior is fall through and no branch needs
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// to be inserted.
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if (!FalseBlock)
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return 1;
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BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
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return 2;
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}
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unsigned LanaiInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator Instruction = MBB.end();
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unsigned Count = 0;
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while (Instruction != MBB.begin()) {
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--Instruction;
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if (Instruction->isDebugValue())
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continue;
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if (Instruction->getOpcode() != Lanai::BT &&
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Instruction->getOpcode() != Lanai::BRCC) {
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break;
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}
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// Remove the branch.
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Instruction->eraseFromParent();
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Instruction = MBB.end();
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++Count;
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}
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return Count;
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}
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unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == Lanai::LDW_RI)
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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return 0;
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}
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unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == Lanai::LDW_RI) {
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unsigned Reg;
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if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
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return Reg;
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// Check for post-frame index elimination operations
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const MachineMemOperand *Dummy;
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return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
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}
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return 0;
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}
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unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == Lanai::SW_RI)
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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return 0;
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}
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bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(
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MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const {
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// Handle only loads/stores with base register followed by immediate offset
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// and with add as ALU op.
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if (LdSt->getNumOperands() != 4)
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return false;
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if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm() ||
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!(LdSt->getOperand(3).isImm() &&
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LdSt->getOperand(3).getImm() == LPAC::ADD))
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return false;
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switch (LdSt->getOpcode()) {
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default:
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return false;
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case Lanai::LDW_RI:
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case Lanai::LDW_RR:
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case Lanai::SW_RR:
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case Lanai::SW_RI:
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Width = 4;
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break;
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STH_RI:
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Width = 2;
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break;
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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case Lanai::STB_RI:
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Width = 1;
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break;
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}
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BaseReg = LdSt->getOperand(1).getReg();
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Offset = LdSt->getOperand(2).getImm();
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return true;
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}
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bool LanaiInstrInfo::getMemOpBaseRegImmOfs(
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MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset,
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const TargetRegisterInfo *TRI) const {
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switch (LdSt->getOpcode()) {
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default:
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return false;
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case Lanai::LDW_RI:
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case Lanai::LDW_RR:
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case Lanai::SW_RR:
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case Lanai::SW_RI:
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STH_RI:
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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unsigned Width;
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return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI);
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}
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}
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