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eecbba2d64
order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247283 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
644 B
YAML
35 lines
644 B
YAML
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define i32 @foo(i32* %p) {
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entry:
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%a = load i32, i32* %p
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%0 = icmp sle i32 %a, 10
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br i1 %0, label %less, label %exit
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less:
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ret i32 0
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exit:
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ret i32 %a
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}
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...
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---
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name: foo
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body: |
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bb.0.entry:
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%eax = MOV32rm %rdi, 1, _, 0, _
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CMP32ri8 %eax, 10, implicit-def %eflags
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; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags'
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JG_1 %bb.2.exit, implicit %eax
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bb.1.less:
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%eax = MOV32r0 implicit-def %eflags
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bb.2.exit:
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RETQ %eax
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...
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