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24517d023f
The current memory-instruction optimization logic in CGP, which sinks parts of
the address computation that can be adsorbed by the addressing mode, does this
by explicitly converting the relevant part of the address computation into
IR-level integer operations (making use of ptrtoint and inttoptr). For most
targets this is currently not a problem, but for targets wishing to make use of
IR-level aliasing analysis during CodeGen, the use of ptrtoint/inttoptr is a
problem for two reasons:
1. BasicAA becomes less powerful in the face of the ptrtoint/inttoptr
2. In cases where type-punning was used, and BasicAA was used
to override TBAA, BasicAA may no longer do so. (this had forced us to disable
all use of TBAA in CodeGen; something which we can now enable again)
This (use of GEPs instead of ptrtoint/inttoptr) is not currently enabled by
default (except for those targets that use AA during CodeGen), and so aside
from some PowerPC subtargets and SystemZ, there should be no change in
behavior. We may be able to switch completely away from the ptrtoint/inttoptr
sinking on all targets, but further testing is required.
I've doubled-up on a number of existing tests that are sensitive to the
address sinking behavior (including some store-merging tests that are
sensitive to the order of the resulting ADD operations at the SDAG level).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206092 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
563 B
LLVM
26 lines
563 B
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -mattr=+v4t -addr-sink-using-gep=1 %s -o - | FileCheck %s
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; <rdar://problem/8686347>
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define i32 @test1(i1 %a, i32* %b) {
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; CHECK: test1
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entry:
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br i1 %a, label %lblock, label %rblock
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lblock:
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%lbranch = getelementptr i32* %b, i32 1
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br label %end
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rblock:
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%rbranch = getelementptr i32* %b, i32 1
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br label %end
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end:
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; CHECK: ldr r0, [r1, #4]
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%gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock]
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%r = load i32* %gep
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; CHECK-NEXT: bx lr
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ret i32 %r
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}
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