mirror of
https://github.com/RPCSX/llvm.git
synced 2025-01-28 15:54:00 +00:00
75834f76b2
Kicks off the implementation of wasm SIMD128 support (spec: https://github.com/stoklund/portable-simd/blob/master/portable-simd.md), adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4. The spec is WIP, and might change in the near future. Patch by João Porto Differential Revision: https://reviews.llvm.org/D22686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277543 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
670 B
TableGen
20 lines
670 B
TableGen
// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
///
|
|
/// \file
|
|
/// \brief WebAssembly SIMD operand code-gen constructs.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let isCommutable = 1 in {
|
|
defm ADD : SIMDBinary<add, fadd, "add ">;
|
|
defm MUL: SIMDBinary<mul, fmul, "mul ">;
|
|
} // isCommutable = 1
|
|
defm SUB: SIMDBinary<sub, fsub, "sub ">;
|