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0b6a44afb9
TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
1098 lines
37 KiB
C++
1098 lines
37 KiB
C++
//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmWriterEmitter.h"
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#include "AsmWriterInst.h"
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#include "Error.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "StringToOffsetTable.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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using namespace llvm;
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static void PrintCases(std::vector<std::pair<std::string,
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AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
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O << " case " << OpsToPrint.back().first << ": ";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ": ";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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}
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// Finally, emit the code.
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O << TheOp.getCode();
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O << "break;\n";
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}
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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raw_ostream &O) {
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AsmWriterInst FirstInst = Insts.back();
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Insts.pop_back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DiffOp != ~1U) {
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
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// If this differs in the same operand as the rest of the instructions in
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// this class, move it to the SimilarInsts list.
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if (DifferingOperand == DiffOp || DiffOp == ~0U) {
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SimilarInsts.push_back(Insts[i-1]);
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Insts.erase(Insts.begin()+i-1);
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}
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}
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}
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O << " case " << FirstInst.CGI->Namespace << "::"
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<< FirstInst.CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
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O << " case " << SimilarInsts[i].CGI->Namespace << "::"
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<< SimilarInsts[i].CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
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if (i != DifferingOperand) {
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// If the operand is the same for all instructions, just print it.
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O << " " << FirstInst.Operands[i].getCode();
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} else {
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// If this is the operand that varies between all of the instructions,
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// emit a switch for just this operand now.
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O << " switch (MI->getOpcode()) {\n";
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std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
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OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
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FirstInst.CGI->TheDef->getName(),
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FirstInst.Operands[i]));
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for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
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AsmWriterInst &AWI = SimilarInsts[si];
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OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
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AWI.CGI->TheDef->getName(),
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AWI.Operands[i]));
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}
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std::reverse(OpsToPrint.begin(), OpsToPrint.end());
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while (!OpsToPrint.empty())
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PrintCases(OpsToPrint, O);
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O << " }";
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}
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O << "\n";
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}
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O << " break;\n";
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}
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void AsmWriterEmitter::
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FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
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std::vector<unsigned> &InstIdxs,
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std::vector<unsigned> &InstOpsUsed) const {
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InstIdxs.assign(NumberedInstructions.size(), ~0U);
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// This vector parallels UniqueOperandCommands, keeping track of which
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// instructions each case are used for. It is a comma separated string of
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// enums.
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std::vector<std::string> InstrsForCase;
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InstrsForCase.resize(UniqueOperandCommands.size());
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InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const AsmWriterInst *Inst = getAsmWriterInstByID(i);
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if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
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std::string Command;
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if (Inst->Operands.empty())
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continue; // Instruction already done.
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Command = " " + Inst->Operands[0].getCode() + "\n";
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// Check to see if we already have 'Command' in UniqueOperandCommands.
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// If not, add it.
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bool FoundIt = false;
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for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
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if (UniqueOperandCommands[idx] == Command) {
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InstIdxs[i] = idx;
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InstrsForCase[idx] += ", ";
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InstrsForCase[idx] += Inst->CGI->TheDef->getName();
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FoundIt = true;
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break;
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}
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if (!FoundIt) {
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InstIdxs[i] = UniqueOperandCommands.size();
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UniqueOperandCommands.push_back(Command);
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InstrsForCase.push_back(Inst->CGI->TheDef->getName());
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// This command matches one operand so far.
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InstOpsUsed.push_back(1);
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}
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}
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// For each entry of UniqueOperandCommands, there is a set of instructions
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// that uses it. If the next command of all instructions in the set are
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// identical, fold it into the command.
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for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
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CommandIdx != e; ++CommandIdx) {
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for (unsigned Op = 1; ; ++Op) {
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// Scan for the first instruction in the set.
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std::vector<unsigned>::iterator NIT =
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std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
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if (NIT == InstIdxs.end()) break; // No commonality.
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// If this instruction has no more operands, we isn't anything to merge
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// into this command.
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const AsmWriterInst *FirstInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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if (!FirstInst || FirstInst->Operands.size() == Op)
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break;
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// Otherwise, scan to see if all of the other instructions in this command
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// set share the operand.
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bool AllSame = true;
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// Keep track of the maximum, number of operands or any
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// instruction we see in the group.
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size_t MaxSize = FirstInst->Operands.size();
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for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
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NIT != InstIdxs.end();
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NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
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// Okay, found another instruction in this command set. If the operand
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// matches, we're ok, otherwise bail out.
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const AsmWriterInst *OtherInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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if (OtherInst &&
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OtherInst->Operands.size() > FirstInst->Operands.size())
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MaxSize = std::max(MaxSize, OtherInst->Operands.size());
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if (!OtherInst || OtherInst->Operands.size() == Op ||
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OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
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AllSame = false;
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break;
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}
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}
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if (!AllSame) break;
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// Okay, everything in this command set has the same next operand. Add it
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// to UniqueOperandCommands and remember that it was consumed.
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std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
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UniqueOperandCommands[CommandIdx] += Command;
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InstOpsUsed[CommandIdx]++;
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}
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}
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// Prepend some of the instructions each case is used for onto the case val.
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for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
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std::string Instrs = InstrsForCase[i];
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if (Instrs.size() > 70) {
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Instrs.erase(Instrs.begin()+70, Instrs.end());
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Instrs += "...";
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}
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if (!Instrs.empty())
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UniqueOperandCommands[i] = " // " + Instrs + "\n" +
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UniqueOperandCommands[i];
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}
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}
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static void UnescapeString(std::string &Str) {
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for (unsigned i = 0; i != Str.size(); ++i) {
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if (Str[i] == '\\' && i != Str.size()-1) {
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switch (Str[i+1]) {
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default: continue; // Don't execute the code after the switch.
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case 'a': Str[i] = '\a'; break;
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case 'b': Str[i] = '\b'; break;
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case 'e': Str[i] = 27; break;
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case 'f': Str[i] = '\f'; break;
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case 'n': Str[i] = '\n'; break;
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case 'r': Str[i] = '\r'; break;
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case 't': Str[i] = '\t'; break;
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case 'v': Str[i] = '\v'; break;
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case '"': Str[i] = '\"'; break;
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case '\'': Str[i] = '\''; break;
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case '\\': Str[i] = '\\'; break;
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}
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// Nuke the second character.
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Str.erase(Str.begin()+i+1);
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}
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}
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}
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/// EmitPrintInstruction - Generate the code for the "printInstruction" method
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/// implementation.
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void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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CodeGenTarget Target(Records);
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter");
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const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr";
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O <<
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"/// printInstruction - This method is automatically generated by tablegen\n"
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"/// from the instruction set description.\n"
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"void " << Target.getName() << ClassName
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<< "::printInstruction(const " << MachineInstrClassName
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<< " *MI, raw_ostream &O) {\n";
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std::vector<AsmWriterInst> Instructions;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I)
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if (!(*I)->AsmString.empty() &&
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(*I)->TheDef->getName() != "PHI")
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Instructions.push_back(
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AsmWriterInst(**I,
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AsmWriter->getValueAsInt("Variant"),
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AsmWriter->getValueAsInt("FirstOperandColumn"),
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AsmWriter->getValueAsInt("OperandSpacing")));
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// Get the instruction numbering.
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NumberedInstructions = Target.getInstructionsByEnumValue();
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// Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
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// all machine instructions are necessarily being printed, so there may be
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// target instructions not in this map.
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for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
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CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
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// Build an aggregate string, and build a table of offsets into it.
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StringToOffsetTable StringTable;
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/// OpcodeInfo - This encodes the index of the string to use for the first
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/// chunk of the output as well as indices used for operand printing.
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std::vector<unsigned> OpcodeInfo;
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unsigned MaxStringIdx = 0;
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
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unsigned Idx;
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if (AWI == 0) {
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// Something not handled by the asmwriter printer.
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Idx = ~0U;
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} else if (AWI->Operands[0].OperandType !=
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AsmWriterOperand::isLiteralTextOperand ||
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AWI->Operands[0].Str.empty()) {
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// Something handled by the asmwriter printer, but with no leading string.
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Idx = StringTable.GetOrAddStringOffset("");
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} else {
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std::string Str = AWI->Operands[0].Str;
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UnescapeString(Str);
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Idx = StringTable.GetOrAddStringOffset(Str);
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MaxStringIdx = std::max(MaxStringIdx, Idx);
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// Nuke the string from the operand list. It is now handled!
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AWI->Operands.erase(AWI->Operands.begin());
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}
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// Bias offset by one since we want 0 as a sentinel.
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OpcodeInfo.push_back(Idx+1);
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}
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// Figure out how many bits we used for the string index.
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unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
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// To reduce code size, we compactify common instructions into a few bits
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// in the opcode-indexed table.
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unsigned BitsLeft = 32-AsmStrBits;
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std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
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while (1) {
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std::vector<std::string> UniqueOperandCommands;
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std::vector<unsigned> InstIdxs;
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std::vector<unsigned> NumInstOpsHandled;
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FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
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NumInstOpsHandled);
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// If we ran out of operands to print, we're done.
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if (UniqueOperandCommands.empty()) break;
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
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// If we don't have enough bits for this operand, don't include it.
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if (NumBits > BitsLeft) {
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DEBUG(errs() << "Not enough bits to densely encode " << NumBits
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<< " more bits\n");
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break;
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}
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// Otherwise, we can include this in the initial lookup table. Add it in.
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BitsLeft -= NumBits;
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for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
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if (InstIdxs[i] != ~0U)
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OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
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// Remove the info about this operand.
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
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if (!Inst->Operands.empty()) {
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unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
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assert(NumOps <= Inst->Operands.size() &&
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"Can't remove this many ops!");
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Inst->Operands.erase(Inst->Operands.begin(),
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Inst->Operands.begin()+NumOps);
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}
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}
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// Remember the handlers for this set of operands.
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TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
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}
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O<<" static const unsigned OpInfo[] = {\n";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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O << " " << OpcodeInfo[i] << "U,\t// "
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<< NumberedInstructions[i]->TheDef->getName() << "\n";
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}
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// Add a dummy entry so the array init doesn't end with a comma.
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O << " 0U\n";
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O << " };\n\n";
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// Emit the string itself.
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O << " const char *AsmStrs = \n";
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StringTable.EmitString(O);
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O << ";\n\n";
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O << " O << \"\\t\";\n\n";
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O << " // Emit the opcode for the instruction.\n"
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<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
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<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
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<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
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// Output the table driven operand information.
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BitsLeft = 32-AsmStrBits;
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for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
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std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(Commands.size());
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assert(NumBits <= BitsLeft && "consistency error");
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// Emit code to extract this field from Bits.
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BitsLeft -= NumBits;
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O << "\n // Fragment " << i << " encoded into " << NumBits
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<< " bits for " << Commands.size() << " unique commands.\n";
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if (Commands.size() == 2) {
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// Emit two possibilitys with if/else.
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O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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<< Commands[1]
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<< " } else {\n"
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<< Commands[0]
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<< " }\n\n";
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} else if (Commands.size() == 1) {
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// Emit a single possibility.
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O << Commands[0] << "\n\n";
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} else {
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O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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<< " default: // unreachable.\n";
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// Print out all the cases.
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for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
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O << " case " << i << ":\n";
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O << Commands[i];
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O << " break;\n";
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}
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O << " }\n\n";
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}
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}
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// Okay, delete instructions with no operand info left.
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for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
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// Entire instruction has been emitted?
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AsmWriterInst &Inst = Instructions[i];
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if (Inst.Operands.empty()) {
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Instructions.erase(Instructions.begin()+i);
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--i; --e;
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}
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}
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// Because this is a vector, we want to emit from the end. Reverse all of the
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// elements in the vector.
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std::reverse(Instructions.begin(), Instructions.end());
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// Now that we've emitted all of the operand info that fit into 32 bits, emit
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// information for those instructions that are left. This is a less dense
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// encoding, but we expect the main 32-bit table to handle the majority of
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// instructions.
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if (!Instructions.empty()) {
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// Find the opcode # of inline asm.
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O << " switch (MI->getOpcode()) {\n";
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while (!Instructions.empty())
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EmitInstructions(Instructions, O);
|
|
|
|
O << " }\n";
|
|
O << " return;\n";
|
|
}
|
|
|
|
O << "}\n";
|
|
}
|
|
|
|
|
|
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
|
|
CodeGenTarget Target(Records);
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
const std::vector<CodeGenRegister*> &Registers =
|
|
Target.getRegBank().getRegisters();
|
|
|
|
StringToOffsetTable StringTable;
|
|
O <<
|
|
"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
|
|
"/// from the register set description. This returns the assembler name\n"
|
|
"/// for the specified register.\n"
|
|
"const char *" << Target.getName() << ClassName
|
|
<< "::getRegisterName(unsigned RegNo) {\n"
|
|
<< " assert(RegNo && RegNo < " << (Registers.size()+1)
|
|
<< " && \"Invalid register number!\");\n"
|
|
<< "\n"
|
|
<< " static const unsigned RegAsmOffset[] = {";
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
const CodeGenRegister &Reg = *Registers[i];
|
|
|
|
std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
|
|
if (AsmName.empty())
|
|
AsmName = Reg.getName();
|
|
|
|
|
|
if ((i % 14) == 0)
|
|
O << "\n ";
|
|
|
|
O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
|
|
}
|
|
O << "0\n"
|
|
<< " };\n"
|
|
<< "\n";
|
|
|
|
O << " const char *AsmStrs =\n";
|
|
StringTable.EmitString(O);
|
|
O << ";\n";
|
|
|
|
O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
|
|
<< "}\n";
|
|
}
|
|
|
|
void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
|
|
CodeGenTarget Target(Records);
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
|
|
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
|
|
Target.getInstructionsByEnumValue();
|
|
|
|
StringToOffsetTable StringTable;
|
|
O <<
|
|
"\n\n#ifdef GET_INSTRUCTION_NAME\n"
|
|
"#undef GET_INSTRUCTION_NAME\n\n"
|
|
"/// getInstructionName: This method is automatically generated by tblgen\n"
|
|
"/// from the instruction set description. This returns the enum name of the\n"
|
|
"/// specified instruction.\n"
|
|
"const char *" << Target.getName() << ClassName
|
|
<< "::getInstructionName(unsigned Opcode) {\n"
|
|
<< " assert(Opcode < " << NumberedInstructions.size()
|
|
<< " && \"Invalid instruction number!\");\n"
|
|
<< "\n"
|
|
<< " static const unsigned InstAsmOffset[] = {";
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
const CodeGenInstruction &Inst = *NumberedInstructions[i];
|
|
|
|
std::string AsmName = Inst.TheDef->getName();
|
|
if ((i % 14) == 0)
|
|
O << "\n ";
|
|
|
|
O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
|
|
}
|
|
O << "0\n"
|
|
<< " };\n"
|
|
<< "\n";
|
|
|
|
O << " const char *Strs =\n";
|
|
StringTable.EmitString(O);
|
|
O << ";\n";
|
|
|
|
O << " return Strs+InstAsmOffset[Opcode];\n"
|
|
<< "}\n\n#endif\n";
|
|
}
|
|
|
|
namespace {
|
|
|
|
/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
|
|
/// feature which participates in instruction matching.
|
|
struct SubtargetFeatureInfo {
|
|
/// \brief The predicate record for this feature.
|
|
const Record *TheDef;
|
|
|
|
/// \brief An unique index assigned to represent this feature.
|
|
unsigned Index;
|
|
|
|
SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
|
|
|
|
/// \brief The name of the enumerated constant identifying this feature.
|
|
std::string getEnumName() const {
|
|
return "Feature_" + TheDef->getName();
|
|
}
|
|
};
|
|
|
|
struct AsmWriterInfo {
|
|
/// Map of Predicate records to their subtarget information.
|
|
std::map<const Record*, SubtargetFeatureInfo*> SubtargetFeatures;
|
|
|
|
/// getSubtargetFeature - Lookup or create the subtarget feature info for the
|
|
/// given operand.
|
|
SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
|
|
assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
|
|
std::map<const Record*, SubtargetFeatureInfo*>::const_iterator I =
|
|
SubtargetFeatures.find(Def);
|
|
return I == SubtargetFeatures.end() ? 0 : I->second;
|
|
}
|
|
|
|
void addReqFeatures(const std::vector<Record*> &Features) {
|
|
for (std::vector<Record*>::const_iterator
|
|
I = Features.begin(), E = Features.end(); I != E; ++I) {
|
|
const Record *Pred = *I;
|
|
|
|
// Ignore predicates that are not intended for the assembler.
|
|
if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
|
|
continue;
|
|
|
|
if (Pred->getName().empty())
|
|
throw TGError(Pred->getLoc(), "Predicate has no name!");
|
|
|
|
// Don't add the predicate again.
|
|
if (getSubtargetFeature(Pred))
|
|
continue;
|
|
|
|
unsigned FeatureNo = SubtargetFeatures.size();
|
|
SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
|
|
assert(FeatureNo < 32 && "Too many subtarget features!");
|
|
}
|
|
}
|
|
|
|
const SubtargetFeatureInfo *getFeatureInfo(const Record *R) {
|
|
return SubtargetFeatures[R];
|
|
}
|
|
};
|
|
|
|
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
|
|
// they both have the same conditionals. In which case, we cannot print out the
|
|
// alias for that pattern.
|
|
class IAPrinter {
|
|
AsmWriterInfo &AWI;
|
|
std::vector<std::string> Conds;
|
|
std::map<StringRef, unsigned> OpMap;
|
|
std::string Result;
|
|
std::string AsmString;
|
|
std::vector<Record*> ReqFeatures;
|
|
public:
|
|
IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS)
|
|
: AWI(Info), Result(R), AsmString(AS) {}
|
|
|
|
void addCond(const std::string &C) { Conds.push_back(C); }
|
|
void addReqFeatures(const std::vector<Record*> &Features) {
|
|
AWI.addReqFeatures(Features);
|
|
ReqFeatures = Features;
|
|
}
|
|
|
|
void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
|
|
unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
|
|
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
|
|
|
|
bool print(raw_ostream &O) {
|
|
if (Conds.empty() && ReqFeatures.empty()) {
|
|
O.indent(6) << "return true;\n";
|
|
return false;
|
|
}
|
|
|
|
O << "if (";
|
|
|
|
for (std::vector<std::string>::iterator
|
|
I = Conds.begin(), E = Conds.end(); I != E; ++I) {
|
|
if (I != Conds.begin()) {
|
|
O << " &&\n";
|
|
O.indent(8);
|
|
}
|
|
|
|
O << *I;
|
|
}
|
|
|
|
if (!ReqFeatures.empty()) {
|
|
if (Conds.begin() != Conds.end()) {
|
|
O << " &&\n";
|
|
O.indent(8);
|
|
} else {
|
|
O << "if (";
|
|
}
|
|
|
|
std::string Req;
|
|
raw_string_ostream ReqO(Req);
|
|
|
|
for (std::vector<Record*>::iterator
|
|
I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) {
|
|
if (I != ReqFeatures.begin()) ReqO << " | ";
|
|
ReqO << AWI.getFeatureInfo(*I)->getEnumName();
|
|
}
|
|
|
|
O << "(AvailableFeatures & (" << ReqO.str() << ")) == ("
|
|
<< ReqO.str() << ')';
|
|
}
|
|
|
|
O << ") {\n";
|
|
O.indent(6) << "// " << Result << "\n";
|
|
O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
|
|
|
|
for (std::map<StringRef, unsigned>::iterator
|
|
I = OpMap.begin(), E = OpMap.end(); I != E; ++I)
|
|
O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", "
|
|
<< I->second << "));\n";
|
|
|
|
O.indent(6) << "break;\n";
|
|
O.indent(4) << '}';
|
|
return !ReqFeatures.empty();
|
|
}
|
|
|
|
bool operator==(const IAPrinter &RHS) {
|
|
if (Conds.size() != RHS.Conds.size())
|
|
return false;
|
|
|
|
unsigned Idx = 0;
|
|
for (std::vector<std::string>::iterator
|
|
I = Conds.begin(), E = Conds.end(); I != E; ++I)
|
|
if (*I != RHS.Conds[Idx++])
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool operator()(const IAPrinter &RHS) {
|
|
if (Conds.size() < RHS.Conds.size())
|
|
return true;
|
|
|
|
unsigned Idx = 0;
|
|
for (std::vector<std::string>::iterator
|
|
I = Conds.begin(), E = Conds.end(); I != E; ++I)
|
|
if (*I != RHS.Conds[Idx++])
|
|
return *I < RHS.Conds[Idx++];
|
|
|
|
return false;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
|
|
/// definitions.
|
|
static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info,
|
|
raw_ostream &O) {
|
|
O << "namespace {\n\n";
|
|
O << "// Flags for subtarget features that participate in "
|
|
<< "alias instruction matching.\n";
|
|
O << "enum SubtargetFeatureFlag {\n";
|
|
|
|
for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
|
|
I = Info.SubtargetFeatures.begin(),
|
|
E = Info.SubtargetFeatures.end(); I != E; ++I) {
|
|
SubtargetFeatureInfo &SFI = *I->second;
|
|
O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
|
|
}
|
|
|
|
O << " Feature_None = 0\n";
|
|
O << "};\n\n";
|
|
O << "} // end anonymous namespace\n\n";
|
|
}
|
|
|
|
/// EmitComputeAvailableFeatures - Emit the function to compute the list of
|
|
/// available features given a subtarget.
|
|
static void EmitComputeAvailableFeatures(AsmWriterInfo &Info,
|
|
Record *AsmWriter,
|
|
CodeGenTarget &Target,
|
|
raw_ostream &O) {
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
|
|
O << "unsigned " << Target.getName() << ClassName << "::\n"
|
|
<< "ComputeAvailableFeatures(const " << Target.getName()
|
|
<< "Subtarget *Subtarget) const {\n";
|
|
O << " unsigned Features = 0;\n";
|
|
|
|
for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
|
|
I = Info.SubtargetFeatures.begin(),
|
|
E = Info.SubtargetFeatures.end(); I != E; ++I) {
|
|
SubtargetFeatureInfo &SFI = *I->second;
|
|
O << " if (" << SFI.TheDef->getValueAsString("CondString")
|
|
<< ")\n";
|
|
O << " Features |= " << SFI.getEnumName() << ";\n";
|
|
}
|
|
|
|
O << " return Features;\n";
|
|
O << "}\n\n";
|
|
}
|
|
|
|
static void EmitGetMapOperandNumber(raw_ostream &O) {
|
|
O << "static unsigned getMapOperandNumber("
|
|
<< "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
|
|
O << " StringRef Name) {\n";
|
|
O << " for (SmallVectorImpl<std::pair<StringRef, unsigned> >::"
|
|
<< "const_iterator\n";
|
|
O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n";
|
|
O << " if (I->first == Name)\n";
|
|
O << " return I->second;\n";
|
|
O << " assert(false && \"Operand not in map!\");\n";
|
|
O << " return 0;\n";
|
|
O << "}\n\n";
|
|
}
|
|
|
|
void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
|
|
CodeGenTarget Target(Records);
|
|
|
|
// Enumerate the register classes.
|
|
const std::vector<CodeGenRegisterClass> &RegisterClasses =
|
|
Target.getRegisterClasses();
|
|
|
|
O << "namespace { // Register classes\n";
|
|
O << " enum RegClass {\n";
|
|
|
|
// Emit the register enum value for each RegisterClass.
|
|
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
|
|
if (I != 0) O << ",\n";
|
|
O << " RC_" << RegisterClasses[I].TheDef->getName();
|
|
}
|
|
|
|
O << "\n };\n";
|
|
O << "} // end anonymous namespace\n\n";
|
|
|
|
// Emit a function that returns 'true' if a regsiter is part of a particular
|
|
// register class. I.e., RAX is part of GR64 on X86.
|
|
O << "static bool regIsInRegisterClass"
|
|
<< "(unsigned RegClass, unsigned Reg) {\n";
|
|
|
|
// Emit the switch that checks if a register belongs to a particular register
|
|
// class.
|
|
O << " switch (RegClass) {\n";
|
|
O << " default: break;\n";
|
|
|
|
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
|
|
const CodeGenRegisterClass &RC = RegisterClasses[I];
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.TheDef->getName();
|
|
O << " case RC_" << Name << ":\n";
|
|
|
|
// Emit the register list now.
|
|
unsigned IE = RC.getOrder().size();
|
|
if (IE == 1) {
|
|
O << " if (Reg == " << getQualifiedName(RC.getOrder()[0]) << ")\n";
|
|
O << " return true;\n";
|
|
} else {
|
|
O << " switch (Reg) {\n";
|
|
O << " default: break;\n";
|
|
|
|
for (unsigned II = 0; II != IE; ++II) {
|
|
Record *Reg = RC.getOrder()[II];
|
|
O << " case " << getQualifiedName(Reg) << ":\n";
|
|
}
|
|
|
|
O << " return true;\n";
|
|
O << " }\n";
|
|
}
|
|
|
|
O << " break;\n";
|
|
}
|
|
|
|
O << " }\n\n";
|
|
O << " return false;\n";
|
|
O << "}\n\n";
|
|
}
|
|
|
|
static unsigned CountNumOperands(StringRef AsmString) {
|
|
unsigned NumOps = 0;
|
|
std::pair<StringRef, StringRef> ASM = AsmString.split(' ');
|
|
|
|
while (!ASM.second.empty()) {
|
|
++NumOps;
|
|
ASM = ASM.second.split(' ');
|
|
}
|
|
|
|
return NumOps;
|
|
}
|
|
|
|
static unsigned CountResultNumOperands(StringRef AsmString) {
|
|
unsigned NumOps = 0;
|
|
std::pair<StringRef, StringRef> ASM = AsmString.split('\t');
|
|
|
|
if (!ASM.second.empty()) {
|
|
size_t I = ASM.second.find('{');
|
|
StringRef Str = ASM.second;
|
|
if (I != StringRef::npos)
|
|
Str = ASM.second.substr(I, ASM.second.find('|', I));
|
|
|
|
ASM = Str.split(' ');
|
|
|
|
do {
|
|
++NumOps;
|
|
ASM = ASM.second.split(' ');
|
|
} while (!ASM.second.empty());
|
|
}
|
|
|
|
return NumOps;
|
|
}
|
|
|
|
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
|
CodeGenTarget Target(Records);
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
|
|
if (!AsmWriter->getValueAsBit("isMCAsmWriter"))
|
|
return;
|
|
|
|
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
|
|
O << "#undef PRINT_ALIAS_INSTR\n\n";
|
|
|
|
EmitRegIsInRegClass(O);
|
|
|
|
// Emit the method that prints the alias instruction.
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
|
|
std::vector<Record*> AllInstAliases =
|
|
Records.getAllDerivedDefinitions("InstAlias");
|
|
|
|
// Create a map from the qualified name to a list of potential matches.
|
|
std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
|
|
for (std::vector<Record*>::iterator
|
|
I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
|
|
CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
|
|
const Record *R = *I;
|
|
if (!R->getValueAsBit("EmitAlias"))
|
|
continue; // We were told not to emit the alias, but to emit the aliasee.
|
|
const DagInit *DI = R->getValueAsDag("ResultInst");
|
|
const DefInit *Op = dynamic_cast<const DefInit*>(DI->getOperator());
|
|
AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
|
|
}
|
|
|
|
// A map of which conditions need to be met for each instruction operand
|
|
// before it can be matched to the mnemonic.
|
|
std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
|
|
AsmWriterInfo AWI;
|
|
|
|
for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
|
|
I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
|
|
std::vector<CodeGenInstAlias*> &Aliases = I->second;
|
|
|
|
for (std::vector<CodeGenInstAlias*>::iterator
|
|
II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
|
|
const CodeGenInstAlias *CGA = *II;
|
|
unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
|
|
unsigned NumResultOps =
|
|
CountResultNumOperands(CGA->ResultInst->AsmString);
|
|
|
|
// Don't emit the alias if it has more operands than what it's aliasing.
|
|
if (NumResultOps < CountNumOperands(CGA->AsmString))
|
|
continue;
|
|
|
|
IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(),
|
|
CGA->AsmString);
|
|
IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates"));
|
|
|
|
std::string Cond;
|
|
Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
|
|
IAP->addCond(Cond);
|
|
|
|
std::map<StringRef, unsigned> OpMap;
|
|
bool CantHandle = false;
|
|
|
|
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
|
|
const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
|
|
|
|
switch (RO.Kind) {
|
|
default: assert(0 && "unexpected InstAlias operand kind");
|
|
case CodeGenInstAlias::ResultOperand::K_Record: {
|
|
const Record *Rec = RO.getRecord();
|
|
StringRef ROName = RO.getName();
|
|
|
|
if (Rec->isSubClassOf("RegisterClass")) {
|
|
Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
|
|
IAP->addCond(Cond);
|
|
|
|
if (!IAP->isOpMapped(ROName)) {
|
|
IAP->addOperand(ROName, i);
|
|
Cond = std::string("regIsInRegisterClass(RC_") +
|
|
CGA->ResultOperands[i].getRecord()->getName() +
|
|
", MI->getOperand(" + llvm::utostr(i) + ").getReg())";
|
|
IAP->addCond(Cond);
|
|
} else {
|
|
Cond = std::string("MI->getOperand(") +
|
|
llvm::utostr(i) + ").getReg() == MI->getOperand(" +
|
|
llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
|
|
IAP->addCond(Cond);
|
|
}
|
|
} else {
|
|
assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
|
|
// FIXME: We may need to handle these situations.
|
|
delete IAP;
|
|
IAP = 0;
|
|
CantHandle = true;
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
case CodeGenInstAlias::ResultOperand::K_Imm:
|
|
Cond = std::string("MI->getOperand(") +
|
|
llvm::utostr(i) + ").getImm() == " +
|
|
llvm::utostr(CGA->ResultOperands[i].getImm());
|
|
IAP->addCond(Cond);
|
|
break;
|
|
case CodeGenInstAlias::ResultOperand::K_Reg:
|
|
Cond = std::string("MI->getOperand(") +
|
|
llvm::utostr(i) + ").getReg() == " + Target.getName() +
|
|
"::" + CGA->ResultOperands[i].getRegister()->getName();
|
|
IAP->addCond(Cond);
|
|
break;
|
|
}
|
|
|
|
if (!IAP) break;
|
|
}
|
|
|
|
if (CantHandle) continue;
|
|
IAPrinterMap[I->first].push_back(IAP);
|
|
}
|
|
}
|
|
|
|
EmitSubtargetFeatureFlagEnumeration(AWI, O);
|
|
EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O);
|
|
|
|
std::string Header;
|
|
raw_string_ostream HeaderO(Header);
|
|
|
|
HeaderO << "bool " << Target.getName() << ClassName
|
|
<< "::printAliasInstr(const MCInst"
|
|
<< " *MI, raw_ostream &OS) {\n";
|
|
|
|
std::string Cases;
|
|
raw_string_ostream CasesO(Cases);
|
|
bool NeedAvailableFeatures = false;
|
|
|
|
for (std::map<std::string, std::vector<IAPrinter*> >::iterator
|
|
I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
|
|
std::vector<IAPrinter*> &IAPs = I->second;
|
|
std::vector<IAPrinter*> UniqueIAPs;
|
|
|
|
for (std::vector<IAPrinter*>::iterator
|
|
II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
|
|
IAPrinter *LHS = *II;
|
|
bool IsDup = false;
|
|
for (std::vector<IAPrinter*>::iterator
|
|
III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
|
|
IAPrinter *RHS = *III;
|
|
if (LHS != RHS && *LHS == *RHS) {
|
|
IsDup = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!IsDup) UniqueIAPs.push_back(LHS);
|
|
}
|
|
|
|
if (UniqueIAPs.empty()) continue;
|
|
|
|
CasesO.indent(2) << "case " << I->first << ":\n";
|
|
|
|
for (std::vector<IAPrinter*>::iterator
|
|
II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
|
|
IAPrinter *IAP = *II;
|
|
CasesO.indent(4);
|
|
NeedAvailableFeatures |= IAP->print(CasesO);
|
|
CasesO << '\n';
|
|
}
|
|
|
|
CasesO.indent(4) << "return false;\n";
|
|
}
|
|
|
|
if (CasesO.str().empty()) {
|
|
O << HeaderO.str();
|
|
O << " return false;\n";
|
|
O << "}\n\n";
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
return;
|
|
}
|
|
|
|
EmitGetMapOperandNumber(O);
|
|
|
|
O << HeaderO.str();
|
|
O.indent(2) << "StringRef AsmString;\n";
|
|
O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
|
|
if (NeedAvailableFeatures)
|
|
O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n";
|
|
O.indent(2) << "switch (MI->getOpcode()) {\n";
|
|
O.indent(2) << "default: return false;\n";
|
|
O << CasesO.str();
|
|
O.indent(2) << "}\n\n";
|
|
|
|
// Code that prints the alias, replacing the operands with the ones from the
|
|
// MCInst.
|
|
O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n";
|
|
O << " OS << '\\t' << ASM.first;\n";
|
|
|
|
O << " if (!ASM.second.empty()) {\n";
|
|
O << " OS << '\\t';\n";
|
|
O << " for (StringRef::iterator\n";
|
|
O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n";
|
|
O << " if (*I == '$') {\n";
|
|
O << " StringRef::iterator Start = ++I;\n";
|
|
O << " while (I != E &&\n";
|
|
O << " ((*I >= 'a' && *I <= 'z') ||\n";
|
|
O << " (*I >= 'A' && *I <= 'Z') ||\n";
|
|
O << " (*I >= '0' && *I <= '9') ||\n";
|
|
O << " *I == '_'))\n";
|
|
O << " ++I;\n";
|
|
O << " StringRef Name(Start, I - Start);\n";
|
|
O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n";
|
|
O << " } else {\n";
|
|
O << " OS << *I++;\n";
|
|
O << " }\n";
|
|
O << " }\n";
|
|
O << " }\n\n";
|
|
|
|
O << " return true;\n";
|
|
O << "}\n\n";
|
|
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
}
|
|
|
|
void AsmWriterEmitter::run(raw_ostream &O) {
|
|
EmitSourceFileHeader("Assembly Writer Source Fragment", O);
|
|
|
|
EmitPrintInstruction(O);
|
|
EmitGetRegisterName(O);
|
|
EmitGetInstructionName(O);
|
|
EmitPrintAliasInstruction(O);
|
|
}
|
|
|