llvm/test/CodeGen
Daniel Sanders b50b4e2d36 [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.
Summary:
-mno-odd-spreg prohibits the use of odd-numbered single-precision floating
point registers. However, vector insert/extract was still using them when
manipulating the subregisters of an MSA register. Fixed this by ensuring
that insertion/extraction is only performed on even-numbered vector
registers when -mno-odd-spreg is given.

Reviewers: vmedic, sstankovic

Reviewed By: sstankovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230235 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-23 17:22:16 +00:00
..
AArch64 AArch64: Safely handle the incoming sret call argument. 2015-02-16 18:10:47 +00:00
ARM [ARM] Re-re-apply VLD1/VST1 base-update combine. 2015-02-19 23:52:41 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. 2015-02-23 17:22:16 +00:00
MSP430
NVPTX
PowerPC I incorrectly marked the VORC instruction as isCommutable when I added it. 2015-02-20 15:54:58 +00:00
R600 R600/SI: Use v_madmk_f32 2015-02-21 21:29:10 +00:00
SPARC SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too 2015-02-16 21:47:58 +00:00
SystemZ [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86 [X86] Add specific mtriple in order to appease builbots 2015-02-23 15:33:40 +00:00
XCore Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-02-20 02:15:36 +00:00