Richard Osborne 62b8786d12 Add instruction encodings / disassembly support 3r instructions. ... It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8		2013-01-20 17:18:47 +00:00
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ARM	Added a option to the disassembler to print immediates as hex.	2012-12-05 18:13:19 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	This is a resubmittal. For some reason it broke the bots yesterday	2013-01-17 00:28:20 +00:00
X86	Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.	2013-01-06 20:39:29 +00:00
XCore	Add instruction encodings / disassembly support 3r instructions.	2013-01-20 17:18:47 +00:00