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f0c3d71794
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304219 91177308-0d34-0410-b5e6-96231b3b80d8
254 lines
10 KiB
LLVM
254 lines
10 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
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; GCN-LABEL: {{^}}load_i8_to_f32:
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; GCN: buffer_load_ubyte [[LOADREG:v[0-9]+]],
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; GCN-NOT: bfe
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; GCN-NOT: lshr
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; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
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; GCN: buffer_store_dword [[CONV]],
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define amdgpu_kernel void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8, i8 addrspace(1)* %in, align 1
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%cvt = uitofp i8 %load to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}load_v2i8_to_v2f32:
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; GCN: buffer_load_ushort [[LD:v[0-9]+]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define amdgpu_kernel void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2
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%cvt = uitofp <2 x i8> %load to <2 x float>
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store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}load_v3i8_to_v3f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: v_cvt_f32_ubyte3_e32
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; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define amdgpu_kernel void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <3 x i8> %load to <3 x float>
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store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}load_v4i8_to_v4f32:
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; GCN: buffer_load_dword [[LOADREG:v[0-9]+]]
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; GCN-NOT: bfe
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; GCN-NOT: lshr
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; GCN-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
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; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
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; GCN: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define amdgpu_kernel void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; This should not be adding instructions to shift into the correct
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; position in the word for the component.
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; FIXME: Packing bytes
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; GCN-LABEL: {{^}}load_v4i8_to_v4f32_unaligned:
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; GCN: buffer_load_ubyte [[LOADREG3:v[0-9]+]]
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; GCN: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
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; GCN: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
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; GCN: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
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; GCN-DAG: v_lshlrev_b32
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; GCN-DAG: v_or_b32
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]],
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}},
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]]
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; Instructions still emitted to repack bytes for add use.
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; GCN-LABEL: {{^}}load_v4i8_to_v4f32_2_uses:
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; GCN: {{buffer|flat}}_load_dword
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; GCN-DAG: v_cvt_f32_ubyte0_e32
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; GCN-DAG: v_cvt_f32_ubyte1_e32
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; GCN-DAG: v_cvt_f32_ubyte2_e32
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; GCN-DAG: v_cvt_f32_ubyte3_e32
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; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24
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; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16
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; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 8
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; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff,
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; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff00,
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; SI-DAG: v_add_i32
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; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffffff00,
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; VI-DAG: v_add_u16_e32
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; VI-DAG: v_add_u16_e32
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; GCN: {{buffer|flat}}_store_dwordx4
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; GCN: {{buffer|flat}}_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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%in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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%add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
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store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
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ret void
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}
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; Make sure this doesn't crash.
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; GCN-LABEL: {{^}}load_v7i8_to_v7f32:
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; GCN: s_endpgm
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define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <7 x i8> %load to <7 x float>
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store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}load_v8i8_to_v8f32:
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; GCN: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
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; GCN-NOT: bfe
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; GCN-NOT: lshr
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; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
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; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
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; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
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; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
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; GCN-NOT: bfe
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; GCN-NOT: lshr
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8
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%cvt = uitofp <8 x i8> %load to <8 x float>
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store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
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; GCN: buffer_load_dword [[LOADREG:v[0-9]+]],
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; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]]
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; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
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; GCN: buffer_store_dword [[CONV]],
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define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32, i32 addrspace(1)* %in, align 4
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%add = add i32 %load, 2
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%inreg = and i32 %add, 255
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%cvt = uitofp i32 %inreg to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
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define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32, i32 addrspace(1)* %in, align 4
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%inreg = and i32 %load, 65280
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%shr = lshr i32 %inreg, 8
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%cvt = uitofp i32 %shr to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; We don't get these ones because of the zext, but instcombine removes
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; them so it shouldn't really matter.
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; GCN-LABEL: {{^}}i8_zext_i32_to_f32:
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define amdgpu_kernel void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8, i8 addrspace(1)* %in, align 1
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%ext = zext i8 %load to i32
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%cvt = uitofp i32 %ext to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32:
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define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
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%ext = zext <4 x i8> %load to <4 x i32>
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%cvt = uitofp <4 x i32> %ext to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}extract_byte0_to_f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: [[VAL]]
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; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[CONV]]
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define amdgpu_kernel void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in
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%and = and i32 %val, 255
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%cvt = uitofp i32 %and to float
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store float %cvt, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}extract_byte1_to_f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: [[VAL]]
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; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[CONV]]
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define amdgpu_kernel void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in
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%srl = lshr i32 %val, 8
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%and = and i32 %srl, 255
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%cvt = uitofp i32 %and to float
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store float %cvt, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}extract_byte2_to_f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: [[VAL]]
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; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[CONV]]
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define amdgpu_kernel void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in
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%srl = lshr i32 %val, 16
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%and = and i32 %srl, 255
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%cvt = uitofp i32 %and to float
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store float %cvt, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}extract_byte3_to_f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN-NOT: [[VAL]]
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; GCN: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[CONV]]
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define amdgpu_kernel void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in
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%srl = lshr i32 %val, 24
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%and = and i32 %srl, 255
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%cvt = uitofp i32 %and to float
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store float %cvt, float addrspace(1)* %out
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ret void
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}
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