Akira Hatanaka 63da689bdf [AArch64] Improve code generation for logical instructions taking ... immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300913, which broke bots because I didn't fix a call to ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of TargetLoweringOpt and TargetLowering. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300930 91177308-0d34-0410-b5e6-96231b3b80d8		2017-04-21 00:05:16 +00:00
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llvm	[AArch64] Improve code generation for logical instructions taking	2017-04-21 00:05:16 +00:00
llvm-c	Introduce LLVMDIBuilderRef	2017-04-20 14:22:47 +00:00