mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-28 07:05:11 +00:00
9ce75625eb
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck %s
|
|
|
|
%struct.F = type { [3 x i8], i8 }
|
|
|
|
@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
|
|
|
|
define void @f1([1 x i32] %f.coerce0) nounwind {
|
|
entry:
|
|
; CHECK: f1
|
|
; CHECK: mov r2, #10
|
|
; CHECK: bfi r1, r2, #22, #4
|
|
%0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
|
|
%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
|
|
%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
|
|
store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
|
|
ret void
|
|
}
|
|
|
|
define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize {
|
|
entry:
|
|
; CHECK: f2
|
|
; CHECK: lsr{{.*}}#7
|
|
; CHECK: bfi r0, r1, #7, #16
|
|
%and = and i32 %A, -8388481 ; <i32> [#uses=1]
|
|
%and2 = and i32 %B, 8388480 ; <i32> [#uses=1]
|
|
%or = or i32 %and2, %and ; <i32> [#uses=1]
|
|
ret i32 %or
|
|
}
|
|
|
|
define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize {
|
|
entry:
|
|
; CHECK: f3
|
|
; CHECK: lsr{{.*}} #7
|
|
; CHECK: mov r0, r1
|
|
; CHECK: bfi r0, r2, #7, #16
|
|
%and = and i32 %A, 8388480 ; <i32> [#uses=1]
|
|
%and2 = and i32 %B, -8388481 ; <i32> [#uses=1]
|
|
%or = or i32 %and2, %and ; <i32> [#uses=1]
|
|
ret i32 %or
|
|
}
|