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14e97c4f51
Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
1.2 KiB
LLVM
32 lines
1.2 KiB
LLVM
; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
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; This test case is a simplified version of an llvm-stress generated test with
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; seed=3718491962.
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; It originally failed on MIPS32 with FP64 with the following error:
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; LLVM ERROR: ran out of registers during register allocation
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; This was caused by impossible register class restrictions caused by the use
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; of BuildPairF64 instead of BuildPairF64_64.
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define void @autogen_SD3718491962() {
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BB:
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; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[02468]}}
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; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[13579]}}
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; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
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; CHECK-FP64-NOT: mtc1 $zero,
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; FIXME: A redundant mthc1 is currently emitted. Add a -NOT when it is
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; eliminated
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%Cmp = fcmp ule double 0.000000e+00, undef
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%Cmp11 = fcmp ueq double 0xFDBD965CF1BB7FDA, undef
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br label %CF88
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CF88: ; preds = %CF86
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%Sl18 = select i1 %Cmp, i1 %Cmp11, i1 %Cmp
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br i1 %Sl18, label %CF88, label %CF85
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CF85: ; preds = %CF88
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ret void
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}
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