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Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
809 B
LLVM
21 lines
809 B
LLVM
; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64
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; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64
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; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64
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declare void @bar(i32*)
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define void @foo(i32 %sz) {
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; ALL-LABEL: foo:
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; M16-NOT: addiu $sp, 0 # 16 bit inst
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; GP32-NOT: addiu $sp, $sp, 0
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; GP64-NOT: daddiu $sp, $sp, 0
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%a = alloca i32, i32 %sz
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call void @bar(i32* %a)
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ret void
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}
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