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afa4193fc8
Fill in the TODO in CodeGenPrepare::OptimizeCallInst so that global variables that are passed to memory intrinsics are aligned in the same way that allocas are. Differential Revision: http://reviews.llvm.org/D8421 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234735 91177308-0d34-0410-b5e6-96231b3b80d8
133 lines
4.9 KiB
LLVM
133 lines
4.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6m-apple-ios -mcpu=cortex-m0 -pre-RA-sched=source -disable-post-ra | FileCheck %s -check-prefix=CHECK-T1
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%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
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@src = external global %struct.x
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@dst = external global %struct.x
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@.str1 = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 1
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@.str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1
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@.str3 = private unnamed_addr constant [24 x i8] c"DHRYSTONE PROGRAM, SOME\00", align 1
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@.str4 = private unnamed_addr constant [18 x i8] c"DHRYSTONE PROGR \00", align 1
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@.str5 = private unnamed_addr constant [7 x i8] c"DHRYST\00", align 1
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@.str6 = private unnamed_addr constant [14 x i8] c"/tmp/rmXXXXXX\00", align 1
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@spool.splbuf = internal global [512 x i8] zeroinitializer, align 16
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define i32 @t0() {
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entry:
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; CHECK-LABEL: t0:
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; CHECK: vldr [[REG1:d[0-9]+]],
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; CHECK: vstr [[REG1]],
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; CHECK-T1-LABEL: t0:
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; CHECK-T1: ldrb [[TREG1:r[0-9]]],
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; CHECK-T1: strb [[TREG1]],
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; CHECK-T1: ldrh [[TREG2:r[0-9]]],
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; CHECK-T1: strh [[TREG2]]
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
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ret i32 0
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}
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define void @t1(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: adds r0, #15
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; CHECK: adds r1, #15
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
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ret void
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}
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define void @t2(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: movw [[REG2:r[0-9]+]], #16716
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; CHECK: movt [[REG2:r[0-9]+]], #72
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; CHECK: str [[REG2]], [r0, #32]
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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ret void
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}
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define void @t3(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vldr d{{[0-9]+}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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ret void
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}
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define void @t4(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: vld1.64 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
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; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
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; CHECK: strh [[REG5:r[0-9]+]], [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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ret void
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}
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define void @t5(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: movs [[REG5:r[0-9]+]], #0
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; CHECK: strb [[REG5]], [r0, #6]
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; CHECK: movw [[REG6:r[0-9]+]], #21587
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; CHECK: strh [[REG6]], [r0, #4]
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; CHECK: movw [[REG7:r[0-9]+]], #18500
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; CHECK: movt [[REG7:r[0-9]+]], #22866
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; CHECK: str [[REG7]]
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; CHECK-T1-LABEL: t5:
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; CHECK-T1: movs [[TREG3:r[0-9]]],
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; CHECK-T1: strb [[TREG3]],
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; CHECK-T1: movs [[TREG4:r[0-9]]],
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; CHECK-T1: strb [[TREG4]],
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
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ret void
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}
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define void @t6() nounwind {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: vldr [[REG9:d[0-9]+]], [r0]
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; CHECK: vstr [[REG9]], [r1]
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; CHECK: adds r1, #6
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; CHECK: adds r0, #6
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; CHECK: vld1.16
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; CHECK: vst1.16
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; CHECK-T1-LABEL: t6:
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; CHECK-T1: movs [[TREG5:r[0-9]]],
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; CHECK-T1: strh [[TREG5]],
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; CHECK-T1: ldr [[TREG6:r[0-9]]],
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; CHECK-T1: str [[TREG6]]
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
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ret void
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}
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%struct.Foo = type { i32, i32, i32, i32 }
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define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: vld1.32
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; CHECK: vst1.32
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; CHECK-T1-LABEL: t7:
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; CHECK-T1: ldr
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; CHECK-T1: str
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%0 = bitcast %struct.Foo* %a to i8*
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%1 = bitcast %struct.Foo* %b to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 16, i32 4, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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