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54eb8ad654
Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276289 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
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; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
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define void @prom_bug(<4 x i8> %t, i16* %p) {
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; SSE2-LABEL: prom_bug:
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; SSE2: ## BB#0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: packuswb %xmm0, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: movw %ax, (%rdi)
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: prom_bug:
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; SSE41: ## BB#0:
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
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; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
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; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)
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; SSE41-NEXT: retq
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%r = bitcast <4 x i8> %t to <2 x i16>
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%o = extractelement <2 x i16> %r, i32 0
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store i16 %o, i16* %p
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ret void
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}
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