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https://github.com/RPCSX/llvm.git
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204c953cd5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
328 lines
13 KiB
LLVM
328 lines
13 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; This test checks that no VGPR to SGPR copies are created by the register
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; allocator.
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; CHECK-LABEL: @phi1
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; CHECK: S_BUFFER_LOAD_DWORD [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0
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; CHECK: V_MOV_B32_e32 v{{[0-9]}}, [[DST]]
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define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
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%23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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%24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
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%25 = fptosi float %23 to i32
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%26 = icmp ne i32 %25, 0
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br i1 %26, label %ENDIF, label %ELSE
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ELSE: ; preds = %main_body
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%27 = fsub float -0.000000e+00, %22
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br label %ENDIF
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ENDIF: ; preds = %main_body, %ELSE
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%temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
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%28 = fadd float %temp.0, %24
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
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ret void
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}
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; Make sure this program doesn't crash
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; CHECK-LABEL: @phi2
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define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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%23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
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%24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
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%25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
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%26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
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%27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
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%28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
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%29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
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%30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
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%31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
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%32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
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%33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
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%34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
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%35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
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%36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
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%37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
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%38 = load <32 x i8> addrspace(2)* %37, !tbaa !1
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%39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
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%40 = load <16 x i8> addrspace(2)* %39, !tbaa !1
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%41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
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%42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
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%43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
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%44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
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%45 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
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%46 = bitcast float %41 to i32
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%47 = bitcast float %42 to i32
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%48 = insertelement <2 x i32> undef, i32 %46, i32 0
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%49 = insertelement <2 x i32> %48, i32 %47, i32 1
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%50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %38, <16 x i8> %40, i32 2)
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%51 = extractelement <4 x float> %50, i32 2
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%52 = call float @fabs(float %51)
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%53 = fmul float %43, %43
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%54 = fmul float %44, %44
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%55 = fadd float %54, %53
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%56 = fmul float %45, %45
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%57 = fadd float %55, %56
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%58 = call float @llvm.AMDGPU.rsq(float %57)
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%59 = fmul float %43, %58
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%60 = fmul float %44, %58
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%61 = fmul float %45, %58
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%62 = fmul float %59, %23
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%63 = fmul float %60, %24
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%64 = fadd float %63, %62
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%65 = fmul float %61, %25
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%66 = fadd float %64, %65
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%67 = fsub float -0.000000e+00, %26
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%68 = fmul float %66, %52
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%69 = fadd float %68, %67
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%70 = fmul float %27, %69
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%71 = fmul float %28, %69
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%72 = call float @fabs(float %70)
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%73 = fcmp olt float 0x3EE4F8B580000000, %72
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%74 = sext i1 %73 to i32
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%75 = bitcast i32 %74 to float
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%76 = bitcast float %75 to i32
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%77 = icmp ne i32 %76, 0
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br i1 %77, label %IF, label %ENDIF
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IF: ; preds = %main_body
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%78 = fsub float -0.000000e+00, %70
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%79 = call float @llvm.AMDIL.exp.(float %78)
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%80 = fsub float -0.000000e+00, %79
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%81 = fadd float 1.000000e+00, %80
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%82 = fdiv float 1.000000e+00, %70
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%83 = fmul float %81, %82
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%84 = fmul float %32, %83
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br label %ENDIF
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ENDIF: ; preds = %main_body, %IF
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%temp4.0 = phi float [ %84, %IF ], [ %32, %main_body ]
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%85 = call float @fabs(float %71)
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%86 = fcmp olt float 0x3EE4F8B580000000, %85
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%87 = sext i1 %86 to i32
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%88 = bitcast i32 %87 to float
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%89 = bitcast float %88 to i32
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%90 = icmp ne i32 %89, 0
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br i1 %90, label %IF25, label %ENDIF24
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IF25: ; preds = %ENDIF
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%91 = fsub float -0.000000e+00, %71
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%92 = call float @llvm.AMDIL.exp.(float %91)
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%93 = fsub float -0.000000e+00, %92
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%94 = fadd float 1.000000e+00, %93
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%95 = fdiv float 1.000000e+00, %71
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%96 = fmul float %94, %95
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%97 = fmul float %36, %96
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br label %ENDIF24
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ENDIF24: ; preds = %ENDIF, %IF25
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%temp8.0 = phi float [ %97, %IF25 ], [ %36, %ENDIF ]
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%98 = fmul float %29, %temp4.0
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%99 = fmul float %30, %temp4.0
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%100 = fmul float %31, %temp4.0
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%101 = fmul float %33, %temp8.0
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%102 = fadd float %101, %98
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%103 = fmul float %34, %temp8.0
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%104 = fadd float %103, %99
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%105 = fmul float %35, %temp8.0
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%106 = fadd float %105, %100
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%107 = call float @llvm.pow.f32(float %52, float %22)
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%108 = fsub float -0.000000e+00, %102
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%109 = fmul float %108, %107
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%110 = fsub float -0.000000e+00, %104
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%111 = fmul float %110, %107
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%112 = fsub float -0.000000e+00, %106
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%113 = fmul float %112, %107
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%114 = call i32 @llvm.SI.packf16(float %109, float %111)
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%115 = bitcast i32 %114 to float
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%116 = call i32 @llvm.SI.packf16(float %113, float 1.000000e+00)
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%117 = bitcast i32 %116 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117)
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ret void
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}
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; We just want ot make sure the program doesn't crash
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; CHECK-LABEL: @loop
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define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !1
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
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%23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
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%24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
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%25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
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%26 = fptosi float %25 to i32
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%27 = bitcast i32 %26 to float
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%28 = bitcast float %27 to i32
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br label %LOOP
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LOOP: ; preds = %ENDIF, %main_body
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%temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
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%temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
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%temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
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%temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
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%29 = bitcast float %temp8.0 to i32
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%30 = icmp sge i32 %29, %28
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%31 = sext i1 %30 to i32
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%32 = bitcast i32 %31 to float
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%33 = bitcast float %32 to i32
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%34 = icmp ne i32 %33, 0
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br i1 %34, label %IF, label %ENDIF
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IF: ; preds = %LOOP
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
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ret void
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ENDIF: ; preds = %LOOP
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%35 = bitcast float %temp8.0 to i32
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%36 = add i32 %35, 1
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%37 = bitcast i32 %36 to float
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br label %LOOP
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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; Function Attrs: readonly
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declare float @fabs(float) #2
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { readonly }
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attributes #3 = { readnone }
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attributes #4 = { nounwind readonly }
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!0 = metadata !{metadata !"const", null}
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!1 = metadata !{metadata !0, metadata !0, i64 0, i32 1}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
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; Function Attrs: readnone
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declare float @llvm.AMDGPU.rsq(float) #3
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; Function Attrs: readnone
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declare float @llvm.AMDIL.exp.(float) #3
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; Function Attrs: nounwind readonly
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declare float @llvm.pow.f32(float, float) #4
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #1
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; This checks for a bug in the FixSGPRCopies pass where VReg96
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; registers were being identified as an SGPR regclass which was causing
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; an assertion failure.
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; CHECK-LABEL: @sample_v3
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; CHECK: IMAGE_SAMPLE
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; CHECK: IMAGE_SAMPLE
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; CHECK: EXP
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; CHECK: S_ENDPGM
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define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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entry:
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%21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
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%22 = load <16 x i8> addrspace(2)* %21, !tbaa !2
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%23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
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%24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
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%25 = load <32 x i8> addrspace(2)* %24, !tbaa !2
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%26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
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%27 = load <16 x i8> addrspace(2)* %26, !tbaa !2
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%28 = fcmp oeq float %23, 0.0
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br i1 %28, label %if, label %else
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if:
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%val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 0, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
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%val.if.0 = extractelement <4 x float> %val.if, i32 0
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%val.if.1 = extractelement <4 x float> %val.if, i32 1
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%val.if.2 = extractelement <4 x float> %val.if, i32 2
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br label %endif
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else:
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%val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 1, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
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%val.else.0 = extractelement <4 x float> %val.else, i32 0
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%val.else.1 = extractelement <4 x float> %val.else, i32 1
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%val.else.2 = extractelement <4 x float> %val.else, i32 2
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br label %endif
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endif:
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%val.0 = phi float [%val.if.0, %if], [%val.else.0, %else]
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%val.1 = phi float [%val.if.1, %if], [%val.else.1, %else]
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%val.2 = phi float [%val.if.2, %if], [%val.else.2, %else]
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0)
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ret void
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}
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!2 = metadata !{metadata !"const", null, i32 1}
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; CHECK-LABEL: @copy1
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; CHECK: BUFFER_LOAD_DWORD
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; CHECK: V_ADD
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; CHECK: S_ENDPGM
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define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
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entry:
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%0 = load float addrspace(1)* %in0
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%1 = fcmp oeq float %0, 0.0
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br i1 %1, label %if0, label %endif
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if0:
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%2 = bitcast float %0 to i32
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%3 = fcmp olt float %0, 0.0
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br i1 %3, label %if1, label %endif
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if1:
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%4 = add i32 %2, 1
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br label %endif
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endif:
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%5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ]
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%6 = bitcast i32 %5 to float
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store float %6, float addrspace(1)* %out
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ret void
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}
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; This test is just checking that we don't crash / assertion fail.
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; CHECK-LABEL: @copy2
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; CHECK: S_ENDPGM
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define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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entry:
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br label %LOOP68
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LOOP68:
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%temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
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%t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
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%g = icmp eq i32 0, %t
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%l = bitcast float %temp4.7 to i32
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br i1 %g, label %IF70, label %ENDIF69
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IF70:
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%q = icmp ne i32 %l, 13
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%temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
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ret void
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ENDIF69:
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%u = add i32 %l, %t
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%v = bitcast i32 %u to float
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%x = add i32 %t, -1
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br label %LOOP68
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}
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attributes #0 = { "ShaderType"="0" }
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