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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
320 lines
12 KiB
C++
320 lines
12 KiB
C++
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates machine instruction PHI nodes by inserting copy
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// instructions. This destroys SSA information, but is the desired input for
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// some register allocators.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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namespace {
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static Statistic<> NumAtomic("phielim", "Number of atomic phis lowered");
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static Statistic<> NumSimple("phielim", "Number of simple phis lowered");
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struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
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bool runOnMachineFunction(MachineFunction &Fn) {
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bool Changed = false;
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// Eliminate PHI instructions by inserting copies into predecessor blocks.
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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Changed |= EliminatePHINodes(Fn, *I);
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return Changed;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
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/// in predecessor basic blocks.
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///
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bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
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void LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt,
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DenseMap<unsigned, VirtReg2IndexFunctor> &VUC);
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};
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RegisterPass<PNE> X("phi-node-elimination",
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"Eliminate PHI nodes for register allocation");
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}
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const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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/// predecessor basic blocks.
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///
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bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
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if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
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return false; // Quick exit for basic blocks without PHIs.
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// VRegPHIUseCount - Keep track of the number of times each virtual register
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// is used by PHI nodes in successors of this block.
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DenseMap<unsigned, VirtReg2IndexFunctor> VRegPHIUseCount;
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VRegPHIUseCount.grow(MF.getSSARegMap()->getLastVirtReg());
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for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin(),
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E = MBB.pred_end(); PI != E; ++PI)
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for (MachineBasicBlock::succ_iterator SI = (*PI)->succ_begin(),
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E = (*PI)->succ_end(); SI != E; ++SI)
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for (MachineBasicBlock::iterator BBI = (*SI)->begin(), E = (*SI)->end();
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BBI != E && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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VRegPHIUseCount[BBI->getOperand(i).getReg()]++;
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// Get an iterator to the first instruction after the last PHI node (this may
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// also be the end of the basic block).
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MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
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while (AfterPHIsIt != MBB.end() &&
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AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
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++AfterPHIsIt; // Skip over all of the PHI nodes...
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while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
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LowerAtomicPHINode(MBB, AfterPHIsIt, VRegPHIUseCount);
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}
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return true;
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}
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/// InstructionUsesRegister - Return true if the specified machine instr has a
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/// use of the specified register.
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static bool InstructionUsesRegister(MachineInstr *MI, unsigned SrcReg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
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if (MI->getOperand(i).isRegister() &&
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MI->getOperand(i).getReg() == SrcReg &&
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MI->getOperand(i).isUse())
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return true;
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return false;
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}
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/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
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/// under the assuption that it needs to be lowered in a way that supports
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/// atomic execution of PHIs. This lowering method is always correct all of the
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/// time.
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void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt,
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DenseMap<unsigned, VirtReg2IndexFunctor> &VRegPHIUseCount) {
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// Unlink the PHI node from the basic block, but don't delete the PHI yet.
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MachineInstr *MPhi = MBB.remove(MBB.begin());
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unsigned DestReg = MPhi->getOperand(0).getReg();
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// Create a new register for the incoming PHI arguments/
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MachineFunction &MF = *MBB.getParent();
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const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
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unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
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// Insert a register to register copy in the top of the current block (but
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// after any remaining phi nodes) which copies the new incoming register
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// into the phi node destination.
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//
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const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
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// Update live variable information if there is any...
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LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
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if (LV) {
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MachineInstr *PHICopy = prior(AfterPHIsIt);
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// Add information to LiveVariables to know that the incoming value is
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// killed. Note that because the value is defined in several places (once
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// each for each incoming block), the "def" block and instruction fields
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// for the VarInfo is not filled in.
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//
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LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
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// Since we are going to be deleting the PHI node, if it is the last use
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// of any registers, or if the value itself is dead, we need to move this
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// information over to the new copy we just inserted.
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//
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LV->removeVirtualRegistersKilled(MPhi);
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// If the result is dead, update LV.
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if (LV->RegisterDefIsDead(MPhi, DestReg)) {
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LV->addVirtualRegisterDead(DestReg, PHICopy);
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LV->removeVirtualRegistersDead(MPhi);
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}
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// Realize that the destination register is defined by the PHI copy now, not
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// the PHI itself.
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LV->getVarInfo(DestReg).DefInst = PHICopy;
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}
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// Adjust the VRegPHIUseCount map to account for the removal of this PHI
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// node.
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unsigned NumPreds = (MPhi->getNumOperands()-1)/2;
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
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VRegPHIUseCount[MPhi->getOperand(i).getReg()] -= NumPreds;
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// Now loop over all of the incoming arguments, changing them to copy into
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// the IncomingReg register in the corresponding predecessor basic block.
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//
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std::set<MachineBasicBlock*> MBBsInsertedInto;
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for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
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unsigned SrcReg = MPhi->getOperand(i-1).getReg();
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assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
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"Machine PHI Operands must all be virtual registers!");
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the
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// source path the PHI.
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MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
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// Check to make sure we haven't already emitted the copy for this block.
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// This can happen because PHI nodes may have multiple entries for the
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// same basic block.
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if (!MBBsInsertedInto.insert(&opBlock).second)
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continue; // If the copy has already been emitted, we're done.
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// Get an iterator pointing to the first terminator in the block (or end()).
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// This is the point where we can insert a copy if we'd like to.
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MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
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// Insert the copy.
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RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
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// Now update live variable information if we have it. Otherwise we're done
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if (!LV) continue;
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// We want to be able to insert a kill of the register if this PHI
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// (aka, the copy we just inserted) is the last use of the source
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// value. Live variable analysis conservatively handles this by
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// saying that the value is live until the end of the block the PHI
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// entry lives in. If the value really is dead at the PHI copy, there
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// will be no successor blocks which have the value live-in.
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//
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// Check to see if the copy is the last use, and if so, update the
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// live variables information so that it knows the copy source
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// instruction kills the incoming value.
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//
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LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
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// Loop over all of the successors of the basic block, checking to see
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// if the value is either live in the block, or if it is killed in the
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// block. Also check to see if this register is in use by another PHI
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// node which has not yet been eliminated. If so, it will be killed
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// at an appropriate point later.
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//
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// Is it used by any PHI instructions in this block?
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bool ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
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std::vector<MachineBasicBlock*> OpSuccBlocks;
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// Otherwise, scan successors, including the BB the PHI node lives in.
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for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
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E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
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MachineBasicBlock *SuccMBB = *SI;
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// Is it alive in this successor?
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unsigned SuccIdx = SuccMBB->getNumber();
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if (SuccIdx < InRegVI.AliveBlocks.size() &&
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InRegVI.AliveBlocks[SuccIdx]) {
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ValueIsLive = true;
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break;
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}
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OpSuccBlocks.push_back(SuccMBB);
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}
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// Check to see if this value is live because there is a use in a successor
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// that kills it.
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if (!ValueIsLive) {
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switch (OpSuccBlocks.size()) {
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case 1: {
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MachineBasicBlock *MBB = OpSuccBlocks[0];
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (InRegVI.Kills[i]->getParent() == MBB) {
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ValueIsLive = true;
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break;
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}
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break;
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}
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case 2: {
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MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1];
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (InRegVI.Kills[i]->getParent() == MBB1 ||
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InRegVI.Kills[i]->getParent() == MBB2) {
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ValueIsLive = true;
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break;
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}
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break;
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}
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default:
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std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
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InRegVI.Kills[i]->getParent())) {
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ValueIsLive = true;
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break;
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}
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}
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}
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// Okay, if we now know that the value is not live out of the block,
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// we can add a kill marker in this block saying that it kills the incoming
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// value!
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if (!ValueIsLive) {
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// In our final twist, we have to decide which instruction kills the
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// register. In most cases this is the copy, however, the first
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// terminator instruction at the end of the block may also use the value.
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// In this case, we should mark *it* as being the killing block, not the
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// copy.
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bool FirstTerminatorUsesValue = false;
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if (I != opBlock.end()) {
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FirstTerminatorUsesValue = InstructionUsesRegister(I, SrcReg);
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// Check that no other terminators use values.
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#ifndef NDEBUG
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for (MachineBasicBlock::iterator TI = next(I); TI != opBlock.end();
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++TI) {
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assert(!InstructionUsesRegister(TI, SrcReg) &&
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"Terminator instructions cannot use virtual registers unless"
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"they are the first terminator in a block!");
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}
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#endif
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}
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MachineBasicBlock::iterator KillInst;
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if (!FirstTerminatorUsesValue)
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KillInst = prior(I);
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else
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KillInst = I;
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// Finally, mark it killed.
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LV->addVirtualRegisterKilled(SrcReg, KillInst);
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// This vreg no longer lives all of the way through opBlock.
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unsigned opBlockNum = opBlock.getNumber();
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if (opBlockNum < InRegVI.AliveBlocks.size())
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InRegVI.AliveBlocks[opBlockNum] = false;
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}
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}
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// Really delete the PHI instruction now!
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delete MPhi;
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++NumAtomic;
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}
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