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77579f5cd8
LLVM has an @llvm.eh.dwarf.cfa intrinsic, used to lower the GCC-compatible __builtin_dwarf_cfa() builtin. As pointed out in PR26761, this is currently broken on PowerPC (and likely on ARM as well). Currently, @llvm.eh.dwarf.cfa is lowered using: ADD(FRAMEADDR, FRAME_TO_ARGS_OFFSET) where FRAME_TO_ARGS_OFFSET defaults to the constant zero. On x86, FRAME_TO_ARGS_OFFSET is lowered to 2*SlotSize. This setup, however, does not work for PowerPC. Because of the way that the stack layout works, the canonical frame address is not exactly (FRAMEADDR + FRAME_TO_ARGS_OFFSET) on PowerPC (there is a lower save-area offset as well), so it is not just a matter of implementing FRAME_TO_ARGS_OFFSET for PowerPC (unless we redefine its semantics -- We can do that, since it is currently used only for @llvm.eh.dwarf.cfa lowering, but the better to directly lower the CFA construct itself (since it can be easily represented as a fixed-offset FrameIndex)). Mips currently does this, but by using a custom lowering for ADD that specifically recognizes the (FRAMEADDR, FRAME_TO_ARGS_OFFSET) pattern. This change introduces a ISD::EH_DWARF_CFA node, which by default expands using the existing logic, but can be directly lowered by the target. Mips is updated to use this method (which simplifies its implementation, and I suspect makes it more robust), and updates PowerPC to do the same. Fixes PR26761. Differential Revision: https://reviews.llvm.org/D24038 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280350 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
649 B
LLVM
29 lines
649 B
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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define void @_Z1fv() #0 {
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entry:
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%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
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call void @_Z1gPv(i8* %0)
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ret void
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; CHECK-LABEL: @_Z1fv
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; CHECK: stdu 1, -[[SS:[0-9]+]](1)
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; CHECK: .cfi_def_cfa_offset [[SS]]
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; CHECK: mr 31, 1
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; CHECK: .cfi_def_cfa_register r31
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; CHECK: addi 3, 31, [[SS]]
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; CHECK-NEXT: bl _Z1gPv
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; CHECK: blr
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}
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declare void @_Z1gPv(i8*)
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; Function Attrs: nounwind
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declare i8* @llvm.eh.dwarf.cfa(i32) #1
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attributes #0 = { "no-frame-pointer-elim"="true" "target-cpu"="ppc64le" }
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attributes #1 = { nounwind }
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