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38caf19333
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277624 91177308-0d34-0410-b5e6-96231b3b80d8
55 lines
2.4 KiB
LLVM
55 lines
2.4 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mcpu=g5 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @foo(float* noalias nocapture %a, float* noalias nocapture %b) #0 {
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vector.ph:
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds float, float* %b, i64 %index
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%1 = bitcast float* %0 to <4 x float>*
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%wide.load = load <4 x float>, <4 x float>* %1, align 4
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%.sum11 = or i64 %index, 4
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%2 = getelementptr float, float* %b, i64 %.sum11
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%3 = bitcast float* %2 to <4 x float>*
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%wide.load8 = load <4 x float>, <4 x float>* %3, align 4
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%4 = fadd <4 x float> %wide.load, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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%5 = fadd <4 x float> %wide.load8, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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%6 = getelementptr inbounds float, float* %a, i64 %index
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%7 = bitcast float* %6 to <4 x float>*
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store <4 x float> %4, <4 x float>* %7, align 4
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%.sum12 = or i64 %index, 4
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%8 = getelementptr float, float* %a, i64 %.sum12
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%9 = bitcast float* %8 to <4 x float>*
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store <4 x float> %5, <4 x float>* %9, align 4
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%index.next = add i64 %index, 8
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%10 = icmp eq i64 %index.next, 16000
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br i1 %10, label %for.end, label %vector.body
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; CHECK: @foo
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; CHECK-DAG: li [[C0:[0-9]+]], 0
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; CHECK-DAG: li [[C15:[0-9]+]], 15
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; CHECK-DAG: lvx [[CNST:[0-9]+]],
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; CHECK: .LBB0_1:
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; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
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; CHECK-DAG: lvsl [[MASK2:[0-9]+]], [[B2:[0-9]+]], [[C0]]
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; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
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; CHECK-DAG: add [[B4:[0-9]+]], [[B2]], [[C0]]
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; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
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; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C15]]
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; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B2]], [[C0]]
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; CHECK-DAG: lvx [[LD4:[0-9]+]], [[B4]], [[C15]]
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; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD3]], [[LD4]], [[MASK2]]
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; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
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; CHECK-DAG: vaddfp {{[0-9]+}}, [[R2]], [[CNST]]
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; CHECK: blr
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for.end: ; preds = %vector.body
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ret void
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}
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attributes #0 = { nounwind }
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