Reed Kotler 6b9d461780 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used ... if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-13 20:28:27 +00:00
..
AArch64	Implement external weak (ELF) symbols on AArch64	2013-02-06 16:43:33 +00:00
ARM	PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA	2013-02-13 19:21:47 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: Add support to generate predicated absolute addressing mode	2013-02-12 16:06:23 +00:00
MBlaze
Mips	For Mips 16, add the optimization where the 16 bit form of addiu sp can be used	2013-02-13 20:28:27 +00:00
MSP430	Add support for varargs functions for msp430.	2012-11-21 17:28:27 +00:00
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	DAGCombiner: Constant folding around pre-increment loads/stores	2013-02-08 21:35:47 +00:00
R600	R600: Add support for SET*_DX10 instructions	2013-02-07 14:02:35 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Use the 'count' attribute to calculate the upper bound of an array.	2012-12-04 21:34:03 +00:00
Thumb2	FileCheck-ify some grep tests	2013-01-25 22:11:46 +00:00
X86	X86: Disable generation of rep;movsl when %esi is used as a base pointer.	2013-02-13 13:40:35 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00