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820985a01b
The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246358 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.8 KiB
LLVM
64 lines
2.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI %s
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; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=CI %s
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@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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; Check that the LDS size emitted correctly
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; EG: .long 166120
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; EG-NEXT: .long 8
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; GCN: .long 47180
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; GCN-NEXT: .long 38792
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; EG: {{^}}local_memory_two_objects:
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; We would like to check the lds writes are using different
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; addresses, but due to variations in the scheduler, we can't do
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; this consistently on evergreen GPUs.
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; EG: LDS_WRITE
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; EG: LDS_WRITE
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; GCN: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
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; GCN-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]]
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; GROUP_BARRIER must be the last instruction in a clause
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; EG: GROUP_BARRIER
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; EG-NEXT: ALU clause
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; Make sure the lds reads are using different addresses, at different
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; constant offsets.
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; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
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; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
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; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
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; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16
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; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]]
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define void @local_memory_two_objects(i32 addrspace(1)* %out) {
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entry:
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
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store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
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%mul = shl nsw i32 %x.i, 1
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%arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
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store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
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%sub = sub nsw i32 3, %x.i
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call void @llvm.AMDGPU.barrier.local()
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%arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
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%0 = load i32, i32 addrspace(3)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i
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store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
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%1 = load i32, i32 addrspace(3)* %arrayidx4, align 4
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%add = add nsw i32 %x.i, 4
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%arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add
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store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local()
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attributes #0 = { readnone }
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