llvm/test/CodeGen/PowerPC/vec_minmax.ll
Kit Barton 40057e8ee8 Add the following 64-bit vector integer arithmetic instructions added in POWER8:
vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-03 19:55:45 +00:00

35 lines
1.3 KiB
LLVM

; Test the vector min/max doubleword instructions added for P8
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
declare <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone
define <2 x i64> @test_vmaxsd(<2 x i64> %x, <2 x i64> %y) {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp
; CHECK: vmaxsd 2, 2, 3
}
define <2 x i64> @test_vmaxud(<2 x i64> %x, <2 x i64> %y) {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp
; CHECK: vmaxud 2, 2, 3
}
define <2 x i64> @test_vminsd(<2 x i64> %x, <2 x i64> %y) {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp
; CHECK: vminsd 2, 2, 3
}
define <2 x i64> @test_vminud(<2 x i64> %x, <2 x i64> %y) {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp
; CHECK: vminud 2, 2, 3
}