mirror of
https://github.com/RPCSX/llvm.git
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7adbf112c7
Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254683 91177308-0d34-0410-b5e6-96231b3b80d8
214 lines
8.3 KiB
LLVM
214 lines
8.3 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s
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;EG-LABEL: {{^}}ashr_v2i32:
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-LABEL: {{^}}ashr_v2i32:
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v2i32:
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = ashr <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v4i32:
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-LABEL: {{^}}ashr_v4i32:
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v4i32:
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = ashr <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_i64:
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;EG: ASHR
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;SI-LABEL: {{^}}ashr_i64:
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;SI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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;VI-LABEL: {{^}}ashr_i64:
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;VI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = sext i32 %in to i64
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%1 = ashr i64 %0, 8
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_i64_2:
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;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
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;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
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;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;SI-LABEL: {{^}}ashr_i64_2:
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI-LABEL: {{^}}ashr_i64_2:
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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%a = load i64, i64 addrspace(1) * %in
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%b = load i64, i64 addrspace(1) * %b_ptr
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%result = ashr i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v2i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: ASHR {{.*}}, [[SHA]]
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;EG-DAG: ASHR {{.*}}, [[SHB]]
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;EG-DAG: LSHR {{.*}}, [[SHA]]
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;EG-DAG: LSHR {{.*}}, [[SHB]]
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;EG-DAG: OR_INT
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;EG-DAG: OR_INT
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ASHR
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;EG-DAG: ASHR
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;SI-LABEL: {{^}}ashr_v2i64:
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v2i64:
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64>, <2 x i64> addrspace(1) * %in
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%b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
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%result = ashr <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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;EG-LABEL: {{^}}ashr_v4i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
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;EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: LSHL {{.*}}, 1
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;EG-DAG: ASHR {{.*}}, [[SHA]]
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;EG-DAG: ASHR {{.*}}, [[SHB]]
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;EG-DAG: ASHR {{.*}}, [[SHC]]
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;EG-DAG: ASHR {{.*}}, [[SHD]]
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;EG-DAG: LSHR {{.*}}, [[SHA]]
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;EG-DAG: LSHR {{.*}}, [[SHB]]
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;EG-DAG: LSHR {{.*}}, [[SHA]]
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;EG-DAG: LSHR {{.*}}, [[SHB]]
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;EG-DAG: OR_INT
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;EG-DAG: OR_INT
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;EG-DAG: OR_INT
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;EG-DAG: OR_INT
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ASHR
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;EG-DAG: ASHR
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;EG-DAG: ASHR
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;EG-DAG: ASHR
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: ASHR {{.*}}, literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;SI-LABEL: {{^}}ashr_v4i64:
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI-LABEL: {{^}}ashr_v4i64:
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
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%a = load <4 x i64>, <4 x i64> addrspace(1) * %in
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%b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
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%result = ashr <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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}
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