Jyotsna Verma 42ba77db53 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-23 21:17:40 +00:00

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AArch64

Replace coff-/elf-dump with llvm-readobj

2013-04-12 04:06:46 +00:00

ARM

Add more tests for r179925 to verify correct handling of signext/zeroext; strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change)

2013-04-23 19:42:25 +00:00

CPP

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Generic

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Hexagon

Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.

2013-04-23 21:17:40 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

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Mips

[mips] In performDSPShiftCombine, check that all elements in the vector are

2013-04-22 19:58:23 +00:00

MSP430

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NVPTX

[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.

2013-03-30 14:29:30 +00:00

PowerPC

Fix PPC optimizeCompareInstr swapped-sub argument handling

2013-04-19 22:08:38 +00:00

R600

R600: Use .AMDGPU.config section to emit stacksize

2013-04-23 17:34:12 +00:00

SI

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SPARC

Cleanup: test source files do not need to be executable

2013-04-22 08:02:43 +00:00

Thumb

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

Thumb2

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X86

Move test from grep to FileCheck.

2013-04-23 12:03:27 +00:00

XCore

[XCore] Extend test to check positve offsets are folded into addresses.

2013-04-16 20:05:52 +00:00