llvm/test/CodeGen/ARM/neon_shift.ll
Bill Wendling a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:00:59 +00:00

12 lines
420 B
LLVM

; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; <rdar://problem/9055897>
define <4 x i16> @t1(<4 x i32> %a) nounwind {
entry:
; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13
%x = tail call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %a, <4 x i32> <i32 -13, i32 -13, i32 -13, i32 -13>)
ret <4 x i16> %x
}
declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone