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7e4cf0a655
Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273271 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc -o - %s -mattr=+macroop-fusion,+use-postra-scheduler | FileCheck %s
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; RUN: llc -o - %s -mcpu=cyclone | FileCheck %s
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target triple = "arm64-apple-ios"
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declare void @foobar(i32 %v0, i32 %v1)
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; Make sure sub is scheduled in front of cbnz
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; CHECK-LABEL: test_sub_cbz:
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; CHECK: add w[[ADDRES:[0-9]+]], w1, #7
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; CHECK: sub w[[SUBRES:[0-9]+]], w0, #13
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; CHECK-NEXT: cbnz w[[SUBRES]], [[SKIPBLOCK:LBB[0-9_]+]]
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; CHECK: mov [[REGTY:[x,w]]]0, [[REGTY]][[ADDRES]]
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; CHECK: mov [[REGTY]]1, [[REGTY]][[SUBRES]]
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; CHECK: bl _foobar
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; CHECK: [[SKIPBLOCK]]:
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; CHECK: mov [[REGTY]]0, [[REGTY]][[SUBRES]]
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; CHECK: mov [[REGTY]]1, [[REGTY]][[ADDRES]]
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; CHECK: bl _foobar
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define void @test_sub_cbz(i32 %a0, i32 %a1) {
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entry:
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; except for the fusion opportunity the sub/add should be equal so the
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; scheduler would leave them in source order if it weren't for the scheduling
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%v0 = sub i32 %a0, 13
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%cond = icmp eq i32 %v0, 0
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%v1 = add i32 %a1, 7
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br i1 %cond, label %if, label %exit
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if:
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call void @foobar(i32 %v1, i32 %v0)
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br label %exit
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exit:
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call void @foobar(i32 %v0, i32 %v1)
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ret void
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}
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