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73fb824626
Changes: - Added disassembler project - Fixed all decoding conflicts in .td files - Added DecoderMethod=“NONE” option to Target.td that allows to disable decoder generation for an instruction. - Created decoding functions for VS_32 and VReg_32 register classes. - Added stubs for decoding all register classes. - Added several tests for disassembler Disassembler only supports: - VI subtarget - VOP1 instruction encoding - 32-bit register operands and inline constants [Valery] One of the point that requires to pay attention to is how decoder conflicts were resolved: - Groups of target instructions were separated by using different DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate approach. - There were conflicts in IMAGE_<> instructions caused by two different reasons: 1. dmask wasn’t specified for the output (fixed) 2. There are image instructions that differ only by the number of the address components but have the same encoding by the HW spec. The actual number of address components is determined by the HW at runtime using image resource descriptor starting from the VGPR encoded in an IMAGE instruction. This means that we should choose only one instruction from conflicting group to be the rule for decoder. I didn’t find the way to disable decoder generation for an arbitrary instruction and therefore made a onelinear fix to tablegen generator that would suppress decoder generation when DecoderMethod is set to “NONE”. This is a change that should be reviewed and submitted first. Otherwise I would need to specify different DecoderNamespace for every instruction in the conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not used in other targets. 3. IMAGE_GATHER decoder generation is for now disabled and to be done later. [/Valery] Patch By: Sam Kolton Differential Revision: http://reviews.llvm.org/D16723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261185 91177308-0d34-0410-b5e6-96231b3b80d8
303 lines
10 KiB
C++
303 lines
10 KiB
C++
//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains definition for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
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#include "AMDGPUDisassembler.h"
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#include "AMDGPU.h"
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#include "AMDGPURegisterInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-disassembler"
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typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenDisassemblerTables.inc"
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &WS,
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raw_ostream &CS) const {
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CommentStream = &CS;
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
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// Try decode 32-bit instruction
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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uint32_t Insn =
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(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
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// Calling the auto-generated decoder function.
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DecodeStatus Result =
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decodeInstruction(DecoderTableVI32, MI, Insn, Address, this, STI);
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if (Result != MCDisassembler::Success) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Size = 4;
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const {
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// ToDo: case 248: 1/(2*PI) - is allowed only on VI
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// ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
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// literal constant.
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switch(Imm) {
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case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
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case 241: F = FloatToBits(-0.5f); return MCDisassembler::Success;
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case 242: F = FloatToBits(1.0f); return MCDisassembler::Success;
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case 243: F = FloatToBits(-1.0f); return MCDisassembler::Success;
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case 244: F = FloatToBits(2.0f); return MCDisassembler::Success;
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case 245: F = FloatToBits(-2.0f); return MCDisassembler::Success;
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case 246: F = FloatToBits(4.0f); return MCDisassembler::Success;
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case 247: F = FloatToBits(-4.0f); return MCDisassembler::Success;
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case 248: F = 0x3e22f983; return MCDisassembler::Success; // 1/(2*PI)
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default: return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,
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int64_t& I) const {
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if ((Imm >= 128) && (Imm <= 192)) {
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I = Imm - 128;
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return MCDisassembler::Success;
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} else if ((Imm >= 193) && (Imm <= 208)) {
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I = 192 - Imm;
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
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unsigned& RegID) const {
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if (Val > 255) {
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return MCDisassembler::Fail;
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}
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RegID = AMDGPUMCRegisterClasses[AMDGPU::VGPR_32RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
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unsigned& RegID) const {
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// ToDo: SI/CI have 104 SGPRs, VI - 102
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if (Val > 101) {
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return MCDisassembler::Fail;
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}
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RegID = AMDGPUMCRegisterClasses[AMDGPU::SGPR_32RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,
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unsigned& RegID) const {
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// ToDo: deal with out-of range registers
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using namespace AMDGPU;
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if (Val <= 101) {
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return DecodeSgprRegister(Val, RegID);
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} else if ((Val >= 256) && (Val <= 511)) {
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return DecodeVgprRegister(Val - 256, RegID);
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} else {
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switch(Val) {
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case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
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case 103: RegID = getMCReg(FLAT_SCR_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for xnack_mask_lo/_hi register
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case 104:
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case 105: return MCDisassembler::Fail;
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case 106: RegID = getMCReg(VCC_LO, STI); return MCDisassembler::Success;
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case 107: RegID = getMCReg(VCC_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for tba_lo/_hi register
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case 108:
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case 109: return MCDisassembler::Fail;
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// ToDo: no support for tma_lo/_hi register
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case 110:
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case 111: return MCDisassembler::Fail;
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// ToDo: no support for ttmp[0:11] register
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case 112:
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case 113:
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case 114:
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case 115:
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case 116:
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case 117:
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case 118:
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case 119:
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case 120:
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case 121:
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case 122:
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case 123: return MCDisassembler::Fail;
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case 124: RegID = getMCReg(M0, STI); return MCDisassembler::Success;
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case 126: RegID = getMCReg(EXEC_LO, STI); return MCDisassembler::Success;
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case 127: RegID = getMCReg(EXEC_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for vccz register
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case 251: return MCDisassembler::Fail;
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// ToDo: no support for execz register
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case 252: return MCDisassembler::Fail;
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case 253: RegID = getMCReg(SCC, STI); return MCDisassembler::Success;
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default: return MCDisassembler::Fail;
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}
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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unsigned RegID;
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if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createReg(RegID));
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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// ToDo: different opcodes allow different formats og this operands
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if ((Imm >= 128) && (Imm <= 208)) {
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// immediate integer
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int64_t Val;
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if (DecodeLitInteger(Imm, Val) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createImm(Val));
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return MCDisassembler::Success;
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}
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} else if ((Imm >= 240) && (Imm <= 248)) {
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// immediate float
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uint32_t Val;
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if (DecodeLitFloat(Imm, Val) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createImm(Val));
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return MCDisassembler::Success;
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}
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} else if (Imm == 254) {
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// LDS direct
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// ToDo: implement LDS direct read
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} else if (Imm == 255) {
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// literal constant
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} else if ((Imm == 125) ||
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((Imm >= 209) && (Imm <= 239)) ||
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(Imm == 249) ||
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(Imm == 250) ||
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(Imm >= 512)) {
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// reserved
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return MCDisassembler::Fail;
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} else {
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// register
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unsigned RegID;
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if (DecodeSrcRegister(Imm, RegID) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createReg(RegID));
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return MCDisassembler::Success;
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}
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}
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return MCDisassembler::Fail;
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}
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static MCDisassembler *createAMDGPUDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new AMDGPUDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeAMDGPUDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
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}
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