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95ba82925b
Found by gcc 6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273322 91177308-0d34-0410-b5e6-96231b3b80d8
664 lines
23 KiB
C++
664 lines
23 KiB
C++
//===--- HexagonOptAddrMode.cpp -------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This implements a Hexagon-specific pass to optimize addressing mode for
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// load/store instructions.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "opt-addr-mode"
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#include "HexagonTargetMachine.h"
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#include "RDFGraph.h"
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#include "RDFLiveness.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
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cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
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"optimization"));
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using namespace llvm;
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using namespace rdf;
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namespace llvm {
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FunctionPass *createHexagonOptAddrMode();
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void initializeHexagonOptAddrModePass(PassRegistry &);
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}
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namespace {
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class HexagonOptAddrMode : public MachineFunctionPass {
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public:
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static char ID;
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HexagonOptAddrMode()
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: MachineFunctionPass(ID), HII(0), MDT(0), DFG(0), LV(0) {
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PassRegistry &R = *PassRegistry::getPassRegistry();
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initializeHexagonOptAddrModePass(R);
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}
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const char *getPassName() const override {
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return "Optimize addressing mode of load/store";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineDominanceFrontier>();
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AU.setPreservesAll();
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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typedef DenseSet<MachineInstr *> MISetType;
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typedef DenseMap<MachineInstr *, bool> InstrEvalMap;
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const HexagonInstrInfo *HII;
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MachineDominatorTree *MDT;
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DataFlowGraph *DFG;
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DataFlowGraph::DefStackMap DefM;
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std::map<RegisterRef, std::map<NodeId, NodeId>> RDefMap;
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Liveness *LV;
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MISetType Deleted;
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bool processBlock(NodeAddr<BlockNode *> BA);
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bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
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NodeAddr<UseNode *> UseN, unsigned UseMOnum);
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bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
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InstrEvalMap &InstrEvalResult, short &SizeInc);
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bool hasRepForm(MachineInstr *MI, unsigned TfrDefR);
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bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr *MI,
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const NodeList &UNodeList);
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void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
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bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
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short getBaseWithLongOffset(const MachineInstr *MI) const;
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void updateMap(NodeAddr<InstrNode *> IA);
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bool constructDefMap(MachineBasicBlock *B);
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bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
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unsigned ImmOpNum);
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bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
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bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI,
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const MachineOperand &ImmOp, unsigned ImmOpNum);
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};
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}
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char HexagonOptAddrMode::ID = 0;
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INITIALIZE_PASS_BEGIN(HexagonOptAddrMode, "opt-amode",
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"Optimize addressing mode", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
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INITIALIZE_PASS_END(HexagonOptAddrMode, "opt-amode", "Optimize addressing mode",
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false, false)
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bool HexagonOptAddrMode::hasRepForm(MachineInstr *MI, unsigned TfrDefR) {
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const MCInstrDesc &MID = MI->getDesc();
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if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(*MI))
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return false;
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if (MID.mayStore()) {
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MachineOperand StOp = MI->getOperand(MI->getNumOperands() - 1);
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if (StOp.isReg() && StOp.getReg() == TfrDefR)
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return false;
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}
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if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
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// Tranform to Absolute plus register offset.
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return (HII->getBaseWithLongOffset(MI) >= 0);
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else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
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// Tranform to absolute addressing mode.
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return (HII->getAbsoluteForm(MI) >= 0);
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return false;
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}
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// Check if addasl instruction can be removed. This is possible only
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// if it's feeding to only load/store instructions with base + register
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// offset as these instruction can be tranformed to use 'absolute plus
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// shifted register offset'.
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// ex:
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// Rs = ##foo
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// Rx = addasl(Rs, Rt, #2)
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// Rd = memw(Rx + #28)
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// Above three instructions can be replaced with Rd = memw(Rt<<#2 + ##foo+28)
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bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
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MachineInstr *MI,
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const NodeList &UNodeList) {
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// check offset size in addasl. if 'offset > 3' return false
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const MachineOperand &OffsetOp = MI->getOperand(3);
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if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
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return false;
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unsigned OffsetReg = MI->getOperand(2).getReg();
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RegisterRef OffsetRR;
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NodeId OffsetRegRD = 0;
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for (NodeAddr<UseNode *> UA : AddAslSN.Addr->members_if(DFG->IsUse, *DFG)) {
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RegisterRef RR = UA.Addr->getRegRef();
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if (OffsetReg == RR.Reg) {
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OffsetRR = RR;
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OffsetRegRD = UA.Addr->getReachingDef();
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}
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}
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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NodeAddr<UseNode *> UA = *I;
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NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
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if ((UA.Addr->getFlags() & NodeAttrs::PhiRef) ||
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RDefMap[OffsetRR][IA.Id] != OffsetRegRD)
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return false;
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MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
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NodeAddr<DefNode *> OffsetRegDN = DFG->addr<DefNode *>(OffsetRegRD);
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// Reaching Def to an offset register can't be a phi.
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if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
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MI->getParent() != UseMI->getParent())
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return false;
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const MCInstrDesc &UseMID = UseMI->getDesc();
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if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
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HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
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getBaseWithLongOffset(UseMI) < 0)
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return false;
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// Addasl output can't be a store value.
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if (UseMID.mayStore() && UseMI->getOperand(2).isReg() &&
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UseMI->getOperand(2).getReg() == MI->getOperand(0).getReg())
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return false;
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for (auto &Mo : UseMI->operands())
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if (Mo.isFI())
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return false;
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}
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return true;
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}
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bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA,
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NodeList &UNodeList) {
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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NodeAddr<UseNode *> UN = *I;
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RegisterRef UR = UN.Addr->getRegRef();
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NodeSet Visited, Defs;
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const auto &ReachingDefs = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
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if (ReachingDefs.size() > 1) {
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DEBUG({
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dbgs() << "*** Multiple Reaching Defs found!!! ***\n";
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for (auto DI : ReachingDefs) {
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NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI);
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NodeAddr<StmtNode *> TempIA = DA.Addr->getOwner(*DFG);
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dbgs() << "\t\t[Reaching Def]: "
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<< Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
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}
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});
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return false;
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}
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}
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return true;
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}
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void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
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NodeList &UNodeList) {
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for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) {
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DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG)
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<< "\n");
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RegisterRef DR = DA.Addr->getRegRef();
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auto UseSet = LV->getAllReachedUses(DR, DA);
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for (auto UI : UseSet) {
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NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI);
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DEBUG({
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NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG);
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dbgs() << "\t\t\t[Reached Use]: "
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<< Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
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});
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if (UA.Addr->getFlags() & NodeAttrs::PhiRef) {
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NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG);
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NodeId id = PA.Id;
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const Liveness::RefMap &phiUse = LV->getRealUses(id);
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DEBUG(dbgs() << "\t\t\t\tphi real Uses"
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<< Print<Liveness::RefMap>(phiUse, *DFG) << "\n");
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if (phiUse.size() > 0) {
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for (auto I : phiUse) {
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if (DR != I.first)
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continue;
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auto phiUseSet = I.second;
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for (auto phiUI : phiUseSet) {
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NodeAddr<UseNode *> phiUA = DFG->addr<UseNode *>(phiUI);
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UNodeList.push_back(phiUA);
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}
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}
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}
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} else
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UNodeList.push_back(UA);
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}
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}
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}
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bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR,
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const NodeList &UNodeList,
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InstrEvalMap &InstrEvalResult,
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short &SizeInc) {
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bool KeepTfr = false;
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bool HasRepInstr = false;
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InstrEvalResult.clear();
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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bool CanBeReplaced = false;
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NodeAddr<UseNode *> UN = *I;
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NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
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MachineInstr *MI = SN.Addr->getCode();
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const MCInstrDesc &MID = MI->getDesc();
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if ((MID.mayLoad() || MID.mayStore())) {
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if (!hasRepForm(MI, tfrDefR)) {
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KeepTfr = true;
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continue;
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}
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SizeInc++;
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CanBeReplaced = true;
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} else if (MI->getOpcode() == Hexagon::S2_addasl_rrri) {
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NodeList AddaslUseList;
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DEBUG(dbgs() << "\nGetting ReachedUses for === " << *MI << "\n");
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getAllRealUses(SN, AddaslUseList);
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// Process phi nodes.
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if (allValidCandidates(SN, AddaslUseList) &&
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canRemoveAddasl(SN, MI, AddaslUseList)) {
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SizeInc += AddaslUseList.size();
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SizeInc -= 1; // Reduce size by 1 as addasl itself can be removed.
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CanBeReplaced = true;
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} else
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SizeInc++;
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} else
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// Currently, only load/store and addasl are handled.
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// Some other instructions to consider -
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// A2_add -> A2_addi
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// M4_mpyrr_addr -> M4_mpyrr_addi
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KeepTfr = true;
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InstrEvalResult[MI] = CanBeReplaced;
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HasRepInstr |= CanBeReplaced;
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}
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// Reduce total size by 2 if original tfr can be deleted.
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if (!KeepTfr)
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SizeInc -= 2;
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return HasRepInstr;
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}
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bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
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unsigned ImmOpNum) {
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bool Changed = false;
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MachineBasicBlock *BB = OldMI->getParent();
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auto UsePos = MachineBasicBlock::iterator(OldMI);
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MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
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++InsertPt;
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unsigned OpStart;
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unsigned OpEnd = OldMI->getNumOperands();
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MachineInstrBuilder MIB;
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if (ImmOpNum == 1) {
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if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
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short NewOpCode = HII->getBaseWithLongOffset(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
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MIB.addOperand(OldMI->getOperand(0));
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MIB.addOperand(OldMI->getOperand(2));
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MIB.addOperand(OldMI->getOperand(3));
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MIB.addOperand(ImmOp);
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OpStart = 4;
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Changed = true;
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} else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
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short NewOpCode = HII->getAbsoluteForm(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
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.addOperand(OldMI->getOperand(0));
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const GlobalValue *GV = ImmOp.getGlobal();
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int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
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MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
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OpStart = 3;
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Changed = true;
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} else
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Changed = false;
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DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
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DEBUG(dbgs() << "[TO]: " << MIB << "\n");
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} else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
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short NewOpCode = HII->xformRegToImmOffset(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
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MIB.addOperand(OldMI->getOperand(0));
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MIB.addOperand(OldMI->getOperand(1));
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MIB.addOperand(ImmOp);
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OpStart = 4;
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Changed = true;
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DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
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DEBUG(dbgs() << "[TO]: " << MIB << "\n");
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}
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if (Changed)
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for (unsigned i = OpStart; i < OpEnd; ++i)
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MIB.addOperand(OldMI->getOperand(i));
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return Changed;
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}
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bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
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unsigned ImmOpNum) {
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bool Changed = false;
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unsigned OpStart;
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unsigned OpEnd = OldMI->getNumOperands();
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MachineBasicBlock *BB = OldMI->getParent();
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auto UsePos = MachineBasicBlock::iterator(OldMI);
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MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
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++InsertPt;
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MachineInstrBuilder MIB;
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if (ImmOpNum == 0) {
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if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
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short NewOpCode = HII->getBaseWithLongOffset(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
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MIB.addOperand(OldMI->getOperand(1));
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MIB.addOperand(OldMI->getOperand(2));
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MIB.addOperand(ImmOp);
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MIB.addOperand(OldMI->getOperand(3));
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OpStart = 4;
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} else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
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short NewOpCode = HII->getAbsoluteForm(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
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const GlobalValue *GV = ImmOp.getGlobal();
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int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm();
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MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
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MIB.addOperand(OldMI->getOperand(2));
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OpStart = 3;
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}
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Changed = true;
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DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
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DEBUG(dbgs() << "[TO]: " << MIB << "\n");
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} else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
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short NewOpCode = HII->xformRegToImmOffset(OldMI);
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assert(NewOpCode >= 0 && "Invalid New opcode\n");
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MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
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MIB.addOperand(OldMI->getOperand(0));
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MIB.addOperand(ImmOp);
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MIB.addOperand(OldMI->getOperand(1));
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OpStart = 2;
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Changed = true;
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DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
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DEBUG(dbgs() << "[TO]: " << MIB << "\n");
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}
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if (Changed)
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for (unsigned i = OpStart; i < OpEnd; ++i)
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MIB.addOperand(OldMI->getOperand(i));
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return Changed;
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}
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short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr *MI) const {
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if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
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short TempOpCode = HII->getBaseWithRegOffset(MI);
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return HII->getBaseWithLongOffset(TempOpCode);
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} else
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return HII->getBaseWithLongOffset(MI);
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}
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bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
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MachineInstr *AddAslMI,
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const MachineOperand &ImmOp,
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unsigned ImmOpNum) {
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NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG);
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DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n");
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NodeList UNodeList;
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getAllRealUses(SA, UNodeList);
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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NodeAddr<UseNode *> UseUN = *I;
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assert(!(UseUN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
"Can't transform this 'AddAsl' instruction!");
|
|
|
|
NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG);
|
|
DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
|
|
<< "\n");
|
|
MachineInstr *UseMI = UseIA.Addr->getCode();
|
|
DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
|
|
<< ">]: " << *UseMI << "\n");
|
|
const MCInstrDesc &UseMID = UseMI->getDesc();
|
|
assert(HII->getAddrMode(UseMI) == HexagonII::BaseImmOffset);
|
|
|
|
auto UsePos = MachineBasicBlock::iterator(UseMI);
|
|
MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
|
|
short NewOpCode = getBaseWithLongOffset(UseMI);
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
unsigned OpStart;
|
|
unsigned OpEnd = UseMI->getNumOperands();
|
|
|
|
MachineBasicBlock *BB = UseMI->getParent();
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
|
|
// change mem(Rs + # ) -> mem(Rt << # + ##)
|
|
if (UseMID.mayLoad()) {
|
|
MIB.addOperand(UseMI->getOperand(0));
|
|
MIB.addOperand(AddAslMI->getOperand(2));
|
|
MIB.addOperand(AddAslMI->getOperand(3));
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
|
MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm(),
|
|
ImmOp.getTargetFlags());
|
|
OpStart = 3;
|
|
} else if (UseMID.mayStore()) {
|
|
MIB.addOperand(AddAslMI->getOperand(2));
|
|
MIB.addOperand(AddAslMI->getOperand(3));
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
|
MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm(),
|
|
ImmOp.getTargetFlags());
|
|
MIB.addOperand(UseMI->getOperand(2));
|
|
OpStart = 3;
|
|
} else
|
|
llvm_unreachable("Unhandled instruction");
|
|
|
|
for (unsigned i = OpStart; i < OpEnd; ++i)
|
|
MIB.addOperand(UseMI->getOperand(i));
|
|
|
|
Deleted.insert(UseMI);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool HexagonOptAddrMode::xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
|
|
NodeAddr<UseNode *> UseN,
|
|
unsigned UseMOnum) {
|
|
const MachineOperand ImmOp = TfrMI->getOperand(1);
|
|
const MCInstrDesc &MID = UseMI->getDesc();
|
|
unsigned Changed = false;
|
|
if (MID.mayLoad())
|
|
Changed = changeLoad(UseMI, ImmOp, UseMOnum);
|
|
else if (MID.mayStore())
|
|
Changed = changeStore(UseMI, ImmOp, UseMOnum);
|
|
else if (UseMI->getOpcode() == Hexagon::S2_addasl_rrri)
|
|
Changed = changeAddAsl(UseN, UseMI, ImmOp, UseMOnum);
|
|
|
|
if (Changed)
|
|
Deleted.insert(UseMI);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
|
|
bool Changed = false;
|
|
|
|
for (auto IA : BA.Addr->members(*DFG)) {
|
|
if (!DFG->IsCode<NodeAttrs::Stmt>(IA))
|
|
continue;
|
|
|
|
NodeAddr<StmtNode *> SA = IA;
|
|
MachineInstr *MI = SA.Addr->getCode();
|
|
if (MI->getOpcode() != Hexagon::A2_tfrsi ||
|
|
!MI->getOperand(1).isGlobal())
|
|
continue;
|
|
|
|
DEBUG(dbgs() << "[Analyzing A2_tfrsi]: " << *MI << "\n");
|
|
DEBUG(dbgs() << "\t[InstrNode]: " << Print<NodeAddr<InstrNode *>>(IA, *DFG)
|
|
<< "\n");
|
|
|
|
NodeList UNodeList;
|
|
getAllRealUses(SA, UNodeList);
|
|
|
|
if (!allValidCandidates(SA, UNodeList))
|
|
continue;
|
|
|
|
short SizeInc = 0;
|
|
unsigned DefR = MI->getOperand(0).getReg();
|
|
InstrEvalMap InstrEvalResult;
|
|
|
|
// Analyze all uses and calculate increase in size. Perform the optimization
|
|
// only if there is no increase in size.
|
|
if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
|
|
continue;
|
|
if (SizeInc > CodeGrowthLimit)
|
|
continue;
|
|
|
|
bool KeepTfr = false;
|
|
|
|
DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n");
|
|
DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n");
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
NodeAddr<UseNode *> UseN = *I;
|
|
assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
"Found a PhiRef node as a real reached use!!");
|
|
|
|
NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
|
|
MachineInstr *UseMI = OwnerN.Addr->getCode();
|
|
DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
|
|
<< ">]: " << *UseMI << "\n");
|
|
|
|
int UseMOnum = -1;
|
|
unsigned NumOperands = UseMI->getNumOperands();
|
|
for (unsigned j = 0; j < NumOperands - 1; ++j) {
|
|
const MachineOperand &op = UseMI->getOperand(j);
|
|
if (op.isReg() && op.isUse() && DefR == op.getReg())
|
|
UseMOnum = j;
|
|
}
|
|
assert(UseMOnum >= 0 && "Invalid reached use!");
|
|
|
|
if (InstrEvalResult[UseMI])
|
|
// Change UseMI if replacement is possible.
|
|
Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum);
|
|
else
|
|
KeepTfr = true;
|
|
}
|
|
if (!KeepTfr)
|
|
Deleted.insert(MI);
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
void HexagonOptAddrMode::updateMap(NodeAddr<InstrNode *> IA) {
|
|
RegisterSet RRs;
|
|
for (NodeAddr<RefNode *> RA : IA.Addr->members(*DFG))
|
|
RRs.insert(RA.Addr->getRegRef());
|
|
bool Common = false;
|
|
for (auto &R : RDefMap) {
|
|
if (!RRs.count(R.first))
|
|
continue;
|
|
Common = true;
|
|
break;
|
|
}
|
|
if (!Common)
|
|
return;
|
|
|
|
for (auto &R : RDefMap) {
|
|
auto F = DefM.find(R.first);
|
|
if (F == DefM.end() || F->second.empty())
|
|
continue;
|
|
R.second[IA.Id] = F->second.top()->Id;
|
|
}
|
|
}
|
|
|
|
bool HexagonOptAddrMode::constructDefMap(MachineBasicBlock *B) {
|
|
bool Changed = false;
|
|
auto BA = DFG->getFunc().Addr->findBlock(B, *DFG);
|
|
DFG->markBlock(BA.Id, DefM);
|
|
|
|
for (NodeAddr<InstrNode *> IA : BA.Addr->members(*DFG)) {
|
|
updateMap(IA);
|
|
DFG->pushDefs(IA, DefM);
|
|
}
|
|
|
|
MachineDomTreeNode *N = MDT->getNode(B);
|
|
for (auto I : *N)
|
|
Changed |= constructDefMap(I->getBlock());
|
|
|
|
DFG->releaseBlock(BA.Id, DefM);
|
|
return Changed;
|
|
}
|
|
|
|
bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
|
|
bool Changed = false;
|
|
auto &HST = MF.getSubtarget<HexagonSubtarget>();
|
|
auto &MRI = MF.getRegInfo();
|
|
HII = HST.getInstrInfo();
|
|
const auto &MDF = getAnalysis<MachineDominanceFrontier>();
|
|
MDT = &getAnalysis<MachineDominatorTree>();
|
|
const auto &TRI = *MF.getSubtarget().getRegisterInfo();
|
|
const TargetOperandInfo TOI(*HII);
|
|
|
|
RegisterAliasInfo RAI(TRI);
|
|
DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, RAI, TOI);
|
|
G.build();
|
|
DFG = &G;
|
|
|
|
Liveness L(MRI, *DFG);
|
|
L.computePhiInfo();
|
|
LV = &L;
|
|
|
|
constructDefMap(&DFG->getMF().front());
|
|
|
|
Deleted.clear();
|
|
NodeAddr<FuncNode *> FA = DFG->getFunc();
|
|
DEBUG(dbgs() << "==== [RefMap#]=====:\n "
|
|
<< Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n");
|
|
|
|
for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
|
|
Changed |= processBlock(BA);
|
|
|
|
for (auto MI : Deleted)
|
|
MI->eraseFromParent();
|
|
|
|
if (Changed) {
|
|
G.build();
|
|
L.computeLiveIns();
|
|
L.resetLiveIns();
|
|
L.resetKills();
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
FunctionPass *llvm::createHexagonOptAddrMode() {
|
|
return new HexagonOptAddrMode();
|
|
}
|