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parsing logic prior to making substantial changes to it. This parsing logic is incredibly wasteful, so I'm planning to rewrite it. Just unittesting the triple parsing logic spends well over 80% of its time in the ARM parsing logic, and others have measured significant time spent here in real production compiles. Stay tuned... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246369 91177308-0d34-0410-b5e6-96231b3b80d8
673 lines
25 KiB
C++
673 lines
25 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include <cctype>
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using namespace llvm;
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namespace {
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// List of canonical FPU names (use getFPUSynonym) and which architectural
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// features they correspond to (use getFPUFeatures).
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// FIXME: TableGen this.
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// The entries must appear in the order listed in ARM::FPUKind for correct indexing
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struct {
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const char * Name;
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ARM::FPUKind ID;
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ARM::FPUVersion FPUVersion;
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ARM::NeonSupportLevel NeonSupport;
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ARM::FPURestriction Restriction;
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} FPUNames[] = {
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{ "invalid", ARM::FK_INVALID, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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{ "none", ARM::FK_NONE, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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{ "vfp", ARM::FK_VFP, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},
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{ "vfpv2", ARM::FK_VFPV2, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},
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{ "vfpv3", ARM::FK_VFPV3, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_None},
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{ "vfpv3-fp16", ARM::FK_VFPV3_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_None},
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{ "vfpv3-d16", ARM::FK_VFPV3_D16, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_D16},
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{ "vfpv3-d16-fp16", ARM::FK_VFPV3_D16_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_D16},
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{ "vfpv3xd", ARM::FK_VFPV3XD, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_SP_D16},
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{ "vfpv3xd-fp16", ARM::FK_VFPV3XD_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_SP_D16},
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{ "vfpv4", ARM::FK_VFPV4, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_None},
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{ "vfpv4-d16", ARM::FK_VFPV4_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_D16},
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{ "fpv4-sp-d16", ARM::FK_FPV4_SP_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_SP_D16},
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{ "fpv5-d16", ARM::FK_FPV5_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_D16},
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{ "fpv5-sp-d16", ARM::FK_FPV5_SP_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_SP_D16},
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{ "fp-armv8", ARM::FK_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_None},
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{ "neon", ARM::FK_NEON, ARM::FV_VFPV3, ARM::NS_Neon, ARM::FR_None},
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{ "neon-fp16", ARM::FK_NEON_FP16, ARM::FV_VFPV3_FP16, ARM::NS_Neon, ARM::FR_None},
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{ "neon-vfpv4", ARM::FK_NEON_VFPV4, ARM::FV_VFPV4, ARM::NS_Neon, ARM::FR_None},
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{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Neon, ARM::FR_None},
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{ "crypto-neon-fp-armv8",
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ARM::FK_CRYPTO_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Crypto, ARM::FR_None},
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{ "softvfp", ARM::FK_SOFTVFP, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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};
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// List of canonical arch names (use getArchSynonym).
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// This table also provides the build attribute fields for CPU arch
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// and Arch ID, according to the Addenda to the ARM ABI, chapters
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// 2.4 and 2.3.5.2 respectively.
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// FIXME: SubArch values were simplified to fit into the expectations
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// of the triples and are not conforming with their official names.
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// Check to see if the expectation should be changed.
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchKind ID;
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const char *CPUAttr; // CPU class in build attributes.
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const char *SubArch; // Sub-Arch name.
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ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
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} ARCHNames[] = {
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{ "invalid", ARM::AK_INVALID, nullptr, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2", ARM::AK_ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2a", ARM::AK_ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv3", ARM::AK_ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv3m", ARM::AK_ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv4", ARM::AK_ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4t", ARM::AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T },
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{ "armv5t", ARM::AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5te", ARM::AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ },
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{ "armv6", ARM::AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6k", ARM::AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K },
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{ "armv6t2", ARM::AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2 },
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{ "armv6z", ARM::AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6-m", ARM::AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv6s-m", ARM::AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M },
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{ "armv7-a", ARM::AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-r", ARM::AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-m", ARM::AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7e-m", ARM::AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M },
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{ "armv8-a", ARM::AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8 },
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// Non-standard Arch names.
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{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE },
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{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE },
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{ "xscale", ARM::AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5", ARM::AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5e", ARM::AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6j", ARM::AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6hl", ARM::AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv7", ARM::AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7l", ARM::AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7hl", ARM::AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7s", ARM::AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7k", ARM::AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7 }
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};
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// List of Arch Extension names.
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// FIXME: TableGen this.
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struct {
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const char *Name;
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unsigned ID;
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} ARCHExtNames[] = {
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{ "invalid", ARM::AEK_INVALID },
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{ "none", ARM::AEK_NONE },
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{ "crc", ARM::AEK_CRC },
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{ "crypto", ARM::AEK_CRYPTO },
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{ "fp", ARM::AEK_FP },
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{ "idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV) },
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{ "mp", ARM::AEK_MP },
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{ "simd", ARM::AEK_SIMD },
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{ "sec", ARM::AEK_SEC },
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{ "virt", ARM::AEK_VIRT },
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{ "os", ARM::AEK_OS },
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{ "iwmmxt", ARM::AEK_IWMMXT },
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{ "iwmmxt2", ARM::AEK_IWMMXT2 },
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{ "maverick", ARM::AEK_MAVERICK },
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{ "xscale", ARM::AEK_XSCALE }
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};
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// List of HWDiv names (use getHWDivSynonym) and which architectural
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// features they correspond to (use getHWDivFeatures).
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// FIXME: TableGen this.
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struct {
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const char *Name;
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unsigned ID;
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} HWDivNames[] = {
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{ "invalid", ARM::AEK_INVALID },
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{ "none", ARM::AEK_NONE },
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{ "thumb", ARM::AEK_HWDIV },
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{ "arm", ARM::AEK_HWDIVARM },
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{ "arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV) }
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};
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// List of CPU names and their arches.
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// The same CPU can have multiple arches and can be default on multiple arches.
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// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
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// When this becomes table-generated, we'd probably need two tables.
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchKind ArchID;
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ARM::FPUKind DefaultFPU;
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bool Default; // is $Name the default CPU for $ArchID ?
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} CPUNames[] = {
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{ "arm2", ARM::AK_ARMV2, ARM::FK_NONE, true },
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{ "arm3", ARM::AK_ARMV2A, ARM::FK_NONE, true },
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{ "arm6", ARM::AK_ARMV3, ARM::FK_NONE, true },
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{ "arm7m", ARM::AK_ARMV3M, ARM::FK_NONE, true },
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{ "arm8", ARM::AK_ARMV4, ARM::FK_NONE, false },
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{ "arm810", ARM::AK_ARMV4, ARM::FK_NONE, false },
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{ "strongarm", ARM::AK_ARMV4, ARM::FK_NONE, true },
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{ "strongarm110", ARM::AK_ARMV4, ARM::FK_NONE, false },
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{ "strongarm1100", ARM::AK_ARMV4, ARM::FK_NONE, false },
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{ "strongarm1110", ARM::AK_ARMV4, ARM::FK_NONE, false },
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{ "arm7tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, true },
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{ "arm7tdmi-s", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm710t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm720t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm9", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm9tdmi", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm920", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm920t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm922t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm940t", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "ep9312", ARM::AK_ARMV4T, ARM::FK_NONE, false },
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{ "arm10tdmi", ARM::AK_ARMV5T, ARM::FK_NONE, true },
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{ "arm1020t", ARM::AK_ARMV5T, ARM::FK_NONE, false },
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{ "arm9e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm946e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm966e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm968e-s", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm10e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm1020e", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm1022e", ARM::AK_ARMV5TE, ARM::FK_NONE, true },
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{ "iwmmxt", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "xscale", ARM::AK_ARMV5TE, ARM::FK_NONE, false },
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{ "arm926ej-s", ARM::AK_ARMV5TEJ, ARM::FK_NONE, true },
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{ "arm1136jf-s", ARM::AK_ARMV6, ARM::FK_VFPV2, true },
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{ "arm1176j-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },
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{ "arm1176jz-s", ARM::AK_ARMV6K, ARM::FK_NONE, false },
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{ "mpcore", ARM::AK_ARMV6K, ARM::FK_VFPV2, false },
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{ "mpcorenovfp", ARM::AK_ARMV6K, ARM::FK_NONE, false },
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{ "arm1176jzf-s", ARM::AK_ARMV6K, ARM::FK_VFPV2, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6Z, ARM::FK_VFPV2, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6ZK, ARM::FK_VFPV2, true },
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{ "arm1156t2-s", ARM::AK_ARMV6T2, ARM::FK_NONE, true },
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{ "arm1156t2f-s", ARM::AK_ARMV6T2, ARM::FK_VFPV2, false },
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{ "cortex-m0", ARM::AK_ARMV6M, ARM::FK_NONE, true },
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{ "cortex-m0plus", ARM::AK_ARMV6M, ARM::FK_NONE, false },
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{ "cortex-m1", ARM::AK_ARMV6M, ARM::FK_NONE, false },
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{ "sc000", ARM::AK_ARMV6M, ARM::FK_NONE, false },
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{ "cortex-a5", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "cortex-a7", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "cortex-a8", ARM::AK_ARMV7A, ARM::FK_NEON, true },
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{ "cortex-a9", ARM::AK_ARMV7A, ARM::FK_NEON_FP16, false },
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{ "cortex-a12", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "cortex-a15", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "cortex-a17", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "krait", ARM::AK_ARMV7A, ARM::FK_NEON_VFPV4, false },
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{ "cortex-r4", ARM::AK_ARMV7R, ARM::FK_NONE, true },
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{ "cortex-r4f", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },
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{ "cortex-r5", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16, false },
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{ "cortex-r7", ARM::AK_ARMV7R, ARM::FK_VFPV3_D16_FP16, false },
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{ "sc300", ARM::AK_ARMV7M, ARM::FK_NONE, false },
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{ "cortex-m3", ARM::AK_ARMV7M, ARM::FK_NONE, true },
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{ "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_FPV4_SP_D16, true },
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{ "cortex-m7", ARM::AK_ARMV7EM, ARM::FK_FPV5_D16, false },
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{ "cortex-a53", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, true },
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{ "cortex-a57", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
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{ "cortex-a72", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
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{ "cyclone", ARM::AK_ARMV8A, ARM::FK_CRYPTO_NEON_FP_ARMV8, false },
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{ "generic", ARM::AK_ARMV8_1A, ARM::FK_NEON_FP_ARMV8, true },
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// Non-standard Arch names.
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{ "iwmmxt", ARM::AK_IWMMXT, ARM::FK_NONE, true },
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{ "xscale", ARM::AK_XSCALE, ARM::FK_NONE, true },
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{ "arm10tdmi", ARM::AK_ARMV5, ARM::FK_NONE, true },
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{ "arm1022e", ARM::AK_ARMV5E, ARM::FK_NONE, true },
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{ "arm1136j-s", ARM::AK_ARMV6J, ARM::FK_NONE, true },
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{ "arm1136jz-s", ARM::AK_ARMV6J, ARM::FK_NONE, false },
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{ "cortex-m0", ARM::AK_ARMV6SM, ARM::FK_NONE, true },
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{ "arm1176jzf-s", ARM::AK_ARMV6HL, ARM::FK_VFPV2, true },
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{ "cortex-a8", ARM::AK_ARMV7, ARM::FK_NEON, true },
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{ "cortex-a8", ARM::AK_ARMV7L, ARM::FK_NEON, true },
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{ "cortex-a8", ARM::AK_ARMV7HL, ARM::FK_NEON, true },
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{ "cortex-m4", ARM::AK_ARMV7EM, ARM::FK_NONE, true },
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{ "swift", ARM::AK_ARMV7S, ARM::FK_NEON_VFPV4, true },
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// Invalid CPU
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{ "invalid", ARM::AK_INVALID, ARM::FK_INVALID, true }
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};
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} // namespace
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// ======================================================= //
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// Information by ID
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// ======================================================= //
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const char *llvm::ARM::getFPUName(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return nullptr;
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return FPUNames[FPUKind].Name;
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}
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unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].FPUVersion;
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}
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unsigned llvm::ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].NeonSupport;
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}
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unsigned llvm::ARM::getFPURestriction(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].Restriction;
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}
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unsigned llvm::ARM::getDefaultFPU(StringRef CPU) {
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for (const auto C : CPUNames) {
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if (CPU == C.Name)
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return C.DefaultFPU;
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}
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return ARM::FK_INVALID;
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}
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bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
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std::vector<const char *> &Features) {
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if (HWDivKind == ARM::AEK_INVALID)
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return false;
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if (HWDivKind & ARM::AEK_HWDIVARM)
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Features.push_back("+hwdiv-arm");
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else
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Features.push_back("-hwdiv-arm");
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if (HWDivKind & ARM::AEK_HWDIV)
|
|
Features.push_back("+hwdiv");
|
|
else
|
|
Features.push_back("-hwdiv");
|
|
|
|
return true;
|
|
}
|
|
|
|
bool llvm::ARM::getFPUFeatures(unsigned FPUKind,
|
|
std::vector<const char *> &Features) {
|
|
|
|
if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID)
|
|
return false;
|
|
|
|
// fp-only-sp and d16 subtarget features are independent of each other, so we
|
|
// must enable/disable both.
|
|
switch (FPUNames[FPUKind].Restriction) {
|
|
case ARM::FR_SP_D16:
|
|
Features.push_back("+fp-only-sp");
|
|
Features.push_back("+d16");
|
|
break;
|
|
case ARM::FR_D16:
|
|
Features.push_back("-fp-only-sp");
|
|
Features.push_back("+d16");
|
|
break;
|
|
case ARM::FR_None:
|
|
Features.push_back("-fp-only-sp");
|
|
Features.push_back("-d16");
|
|
break;
|
|
}
|
|
|
|
// FPU version subtarget features are inclusive of lower-numbered ones, so
|
|
// enable the one corresponding to this version and disable all that are
|
|
// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
|
|
// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
|
|
switch (FPUNames[FPUKind].FPUVersion) {
|
|
case ARM::FV_VFPV5:
|
|
Features.push_back("+fp-armv8");
|
|
break;
|
|
case ARM::FV_VFPV4:
|
|
Features.push_back("+vfp4");
|
|
Features.push_back("-fp-armv8");
|
|
break;
|
|
case ARM::FV_VFPV3_FP16:
|
|
Features.push_back("+vfp3");
|
|
Features.push_back("+fp16");
|
|
Features.push_back("-vfp4");
|
|
Features.push_back("-fp-armv8");
|
|
break;
|
|
case ARM::FV_VFPV3:
|
|
Features.push_back("+vfp3");
|
|
Features.push_back("-fp16");
|
|
Features.push_back("-vfp4");
|
|
Features.push_back("-fp-armv8");
|
|
break;
|
|
case ARM::FV_VFPV2:
|
|
Features.push_back("+vfp2");
|
|
Features.push_back("-vfp3");
|
|
Features.push_back("-fp16");
|
|
Features.push_back("-vfp4");
|
|
Features.push_back("-fp-armv8");
|
|
break;
|
|
case ARM::FV_NONE:
|
|
Features.push_back("-vfp2");
|
|
Features.push_back("-vfp3");
|
|
Features.push_back("-fp16");
|
|
Features.push_back("-vfp4");
|
|
Features.push_back("-fp-armv8");
|
|
break;
|
|
}
|
|
|
|
// crypto includes neon, so we handle this similarly to FPU version.
|
|
switch (FPUNames[FPUKind].NeonSupport) {
|
|
case ARM::NS_Crypto:
|
|
Features.push_back("+crypto");
|
|
break;
|
|
case ARM::NS_Neon:
|
|
Features.push_back("+neon");
|
|
Features.push_back("-crypto");
|
|
break;
|
|
case ARM::NS_None:
|
|
Features.push_back("-neon");
|
|
Features.push_back("-crypto");
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
const char *llvm::ARM::getArchName(unsigned ArchKind) {
|
|
if (ArchKind >= ARM::AK_LAST)
|
|
return nullptr;
|
|
return ARCHNames[ArchKind].Name;
|
|
}
|
|
|
|
const char *llvm::ARM::getCPUAttr(unsigned ArchKind) {
|
|
if (ArchKind >= ARM::AK_LAST)
|
|
return nullptr;
|
|
return ARCHNames[ArchKind].CPUAttr;
|
|
}
|
|
|
|
const char *llvm::ARM::getSubArch(unsigned ArchKind) {
|
|
if (ArchKind >= ARM::AK_LAST)
|
|
return nullptr;
|
|
return ARCHNames[ArchKind].SubArch;
|
|
}
|
|
|
|
unsigned llvm::ARM::getArchAttr(unsigned ArchKind) {
|
|
if (ArchKind >= ARM::AK_LAST)
|
|
return ARMBuildAttrs::CPUArch::Pre_v4;
|
|
return ARCHNames[ArchKind].ArchAttr;
|
|
}
|
|
|
|
const char *llvm::ARM::getArchExtName(unsigned ArchExtKind) {
|
|
for (const auto AE : ARCHExtNames) {
|
|
if (ArchExtKind == AE.ID)
|
|
return AE.Name;
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
const char *llvm::ARM::getHWDivName(unsigned HWDivKind) {
|
|
for (const auto D : HWDivNames) {
|
|
if (HWDivKind == D.ID)
|
|
return D.Name;
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
const char *llvm::ARM::getDefaultCPU(StringRef Arch) {
|
|
unsigned AK = parseArch(Arch);
|
|
if (AK == ARM::AK_INVALID)
|
|
return nullptr;
|
|
|
|
// Look for multiple AKs to find the default for pair AK+Name.
|
|
for (const auto CPU : CPUNames) {
|
|
if (CPU.ArchID == AK && CPU.Default)
|
|
return CPU.Name;
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
// ======================================================= //
|
|
// Parsers
|
|
// ======================================================= //
|
|
|
|
static StringRef getHWDivSynonym(StringRef HWDiv) {
|
|
return StringSwitch<StringRef>(HWDiv)
|
|
.Case("thumb,arm", "arm,thumb")
|
|
.Default(HWDiv);
|
|
}
|
|
|
|
static StringRef getFPUSynonym(StringRef FPU) {
|
|
return StringSwitch<StringRef>(FPU)
|
|
.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
|
|
.Case("vfp2", "vfpv2")
|
|
.Case("vfp3", "vfpv3")
|
|
.Case("vfp4", "vfpv4")
|
|
.Case("vfp3-d16", "vfpv3-d16")
|
|
.Case("vfp4-d16", "vfpv4-d16")
|
|
.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
|
|
.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
|
|
.Case("fp5-sp-d16", "fpv5-sp-d16")
|
|
.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
|
|
// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
|
|
.Case("neon-vfpv3", "neon")
|
|
.Default(FPU);
|
|
}
|
|
|
|
static StringRef getArchSynonym(StringRef Arch) {
|
|
return StringSwitch<StringRef>(Arch)
|
|
.Case("v6sm", "v6s-m")
|
|
.Case("v6m", "v6-m")
|
|
.Case("v7a", "v7-a")
|
|
.Case("v7r", "v7-r")
|
|
.Case("v7m", "v7-m")
|
|
.Case("v7em", "v7e-m")
|
|
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
|
|
.Case("v8.1a", "v8.1-a")
|
|
.Default(Arch);
|
|
}
|
|
|
|
// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
|
|
// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
|
|
// "v.+", if the latter, return unmodified string, minus 'eb'.
|
|
// If invalid, return empty string.
|
|
StringRef llvm::ARM::getCanonicalArchName(StringRef Arch) {
|
|
size_t offset = StringRef::npos;
|
|
StringRef A = Arch;
|
|
StringRef Error = "";
|
|
|
|
// Begins with "arm" / "thumb", move past it.
|
|
if (A.startswith("arm64"))
|
|
offset = 5;
|
|
else if (A.startswith("arm"))
|
|
offset = 3;
|
|
else if (A.startswith("thumb"))
|
|
offset = 5;
|
|
else if (A.startswith("aarch64")) {
|
|
offset = 7;
|
|
// AArch64 uses "_be", not "eb" suffix.
|
|
if (A.find("eb") != StringRef::npos)
|
|
return Error;
|
|
if (A.substr(offset, 3) == "_be")
|
|
offset += 3;
|
|
}
|
|
|
|
// Ex. "armebv7", move past the "eb".
|
|
if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
|
|
offset += 2;
|
|
// Or, if it ends with eb ("armv7eb"), chop it off.
|
|
else if (A.endswith("eb"))
|
|
A = A.substr(0, A.size() - 2);
|
|
// Trim the head
|
|
if (offset != StringRef::npos)
|
|
A = A.substr(offset);
|
|
|
|
// Empty string means offset reached the end, which means it's valid.
|
|
if (A.empty())
|
|
return Arch;
|
|
|
|
// Only match non-marketing names
|
|
if (offset != StringRef::npos) {
|
|
// Must start with 'vN'.
|
|
if (A[0] != 'v' || !std::isdigit(A[1]))
|
|
return Error;
|
|
// Can't have an extra 'eb'.
|
|
if (A.find("eb") != StringRef::npos)
|
|
return Error;
|
|
}
|
|
|
|
// Arch will either be a 'v' name (v7a) or a marketing name (xscale).
|
|
return A;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseHWDiv(StringRef HWDiv) {
|
|
StringRef Syn = getHWDivSynonym(HWDiv);
|
|
for (const auto D : HWDivNames) {
|
|
if (Syn == D.Name)
|
|
return D.ID;
|
|
}
|
|
return ARM::AEK_INVALID;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseFPU(StringRef FPU) {
|
|
StringRef Syn = getFPUSynonym(FPU);
|
|
for (const auto F : FPUNames) {
|
|
if (Syn == F.Name)
|
|
return F.ID;
|
|
}
|
|
return ARM::FK_INVALID;
|
|
}
|
|
|
|
// Allows partial match, ex. "v7a" matches "armv7a".
|
|
unsigned llvm::ARM::parseArch(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
StringRef Syn = getArchSynonym(Arch);
|
|
for (const auto A : ARCHNames) {
|
|
if (StringRef(A.Name).endswith(Syn))
|
|
return A.ID;
|
|
}
|
|
return ARM::AK_INVALID;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseArchExt(StringRef ArchExt) {
|
|
for (const auto A : ARCHExtNames) {
|
|
if (ArchExt == A.Name)
|
|
return A.ID;
|
|
}
|
|
return ARM::AEK_INVALID;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseCPUArch(StringRef CPU) {
|
|
for (const auto C : CPUNames) {
|
|
if (CPU == C.Name)
|
|
return C.ArchID;
|
|
}
|
|
return ARM::AK_INVALID;
|
|
}
|
|
|
|
// ARM, Thumb, AArch64
|
|
unsigned llvm::ARM::parseArchISA(StringRef Arch) {
|
|
return StringSwitch<unsigned>(Arch)
|
|
.StartsWith("aarch64", ARM::IK_AARCH64)
|
|
.StartsWith("arm64", ARM::IK_AARCH64)
|
|
.StartsWith("thumb", ARM::IK_THUMB)
|
|
.StartsWith("arm", ARM::IK_ARM)
|
|
.Default(ARM::EK_INVALID);
|
|
}
|
|
|
|
// Little/Big endian
|
|
unsigned llvm::ARM::parseArchEndian(StringRef Arch) {
|
|
if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
|
|
Arch.startswith("aarch64_be"))
|
|
return ARM::EK_BIG;
|
|
|
|
if (Arch.startswith("arm") || Arch.startswith("thumb")) {
|
|
if (Arch.endswith("eb"))
|
|
return ARM::EK_BIG;
|
|
else
|
|
return ARM::EK_LITTLE;
|
|
}
|
|
|
|
if (Arch.startswith("aarch64"))
|
|
return ARM::EK_LITTLE;
|
|
|
|
return ARM::EK_INVALID;
|
|
}
|
|
|
|
// Profile A/R/M
|
|
unsigned llvm::ARM::parseArchProfile(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::AK_ARMV6M:
|
|
case ARM::AK_ARMV7M:
|
|
case ARM::AK_ARMV6SM:
|
|
case ARM::AK_ARMV7EM:
|
|
return ARM::PK_M;
|
|
case ARM::AK_ARMV7R:
|
|
return ARM::PK_R;
|
|
case ARM::AK_ARMV7:
|
|
case ARM::AK_ARMV7A:
|
|
case ARM::AK_ARMV7L:
|
|
case ARM::AK_ARMV8A:
|
|
case ARM::AK_ARMV8_1A:
|
|
return ARM::PK_A;
|
|
}
|
|
return ARM::PK_INVALID;
|
|
}
|
|
|
|
// Version number (ex. v7 = 7).
|
|
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::AK_ARMV2:
|
|
case ARM::AK_ARMV2A:
|
|
return 2;
|
|
case ARM::AK_ARMV3:
|
|
case ARM::AK_ARMV3M:
|
|
return 3;
|
|
case ARM::AK_ARMV4:
|
|
case ARM::AK_ARMV4T:
|
|
return 4;
|
|
case ARM::AK_ARMV5:
|
|
case ARM::AK_ARMV5T:
|
|
case ARM::AK_ARMV5TE:
|
|
case ARM::AK_IWMMXT:
|
|
case ARM::AK_IWMMXT2:
|
|
case ARM::AK_XSCALE:
|
|
case ARM::AK_ARMV5E:
|
|
case ARM::AK_ARMV5TEJ:
|
|
return 5;
|
|
case ARM::AK_ARMV6:
|
|
case ARM::AK_ARMV6J:
|
|
case ARM::AK_ARMV6K:
|
|
case ARM::AK_ARMV6T2:
|
|
case ARM::AK_ARMV6Z:
|
|
case ARM::AK_ARMV6ZK:
|
|
case ARM::AK_ARMV6M:
|
|
case ARM::AK_ARMV6SM:
|
|
case ARM::AK_ARMV6HL:
|
|
return 6;
|
|
case ARM::AK_ARMV7:
|
|
case ARM::AK_ARMV7A:
|
|
case ARM::AK_ARMV7R:
|
|
case ARM::AK_ARMV7M:
|
|
case ARM::AK_ARMV7L:
|
|
case ARM::AK_ARMV7HL:
|
|
case ARM::AK_ARMV7S:
|
|
case ARM::AK_ARMV7EM:
|
|
case ARM::AK_ARMV7K:
|
|
return 7;
|
|
case ARM::AK_ARMV8A:
|
|
case ARM::AK_ARMV8_1A:
|
|
return 8;
|
|
}
|
|
return 0;
|
|
}
|