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759ed7e410
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273652 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
8.3 KiB
C++
265 lines
8.3 KiB
C++
//===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements hazard recognizers for scheduling on GCN processors.
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//
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//===----------------------------------------------------------------------===//
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#include "GCNHazardRecognizer.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Hazard Recoginizer Implementation
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//===----------------------------------------------------------------------===//
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GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF) :
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CurrCycleInstr(nullptr),
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MF(MF),
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ST(MF.getSubtarget<SISubtarget>()) {
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MaxLookAhead = 5;
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}
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void GCNHazardRecognizer::EmitInstruction(SUnit *SU) {
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EmitInstruction(SU->getInstr());
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}
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void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) {
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CurrCycleInstr = MI;
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}
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ScheduleHazardRecognizer::HazardType
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GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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MachineInstr *MI = SU->getInstr();
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if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0)
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return NoopHazard;
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if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
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return NoopHazard;
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if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
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return NoopHazard;
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return NoHazard;
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}
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unsigned GCNHazardRecognizer::PreEmitNoops(SUnit *SU) {
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return PreEmitNoops(SU->getInstr());
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}
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unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
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if (SIInstrInfo::isSMRD(*MI))
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return std::max(0, checkSMRDHazards(MI));
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if (SIInstrInfo::isVMEM(*MI))
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return std::max(0, checkVMEMHazards(MI));
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if (SIInstrInfo::isDPP(*MI))
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return std::max(0, checkDPPHazards(MI));
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return 0;
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}
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void GCNHazardRecognizer::EmitNoop() {
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EmittedInstrs.push_front(nullptr);
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}
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void GCNHazardRecognizer::AdvanceCycle() {
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// When the scheduler detects a stall, it will call AdvanceCycle() without
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// emitting any instructions.
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if (!CurrCycleInstr)
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return;
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const SIInstrInfo *TII = ST.getInstrInfo();
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unsigned NumWaitStates = TII->getNumWaitStates(*CurrCycleInstr);
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// Keep track of emitted instructions
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EmittedInstrs.push_front(CurrCycleInstr);
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// Add a nullptr for each additional wait state after the first. Make sure
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// not to add more than getMaxLookAhead() items to the list, since we
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// truncate the list to that size right after this loop.
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for (unsigned i = 1, e = std::min(NumWaitStates, getMaxLookAhead());
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i < e; ++i) {
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EmittedInstrs.push_front(nullptr);
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}
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// getMaxLookahead() is the largest number of wait states we will ever need
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// to insert, so there is no point in keeping track of more than that many
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// wait states.
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EmittedInstrs.resize(getMaxLookAhead());
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CurrCycleInstr = nullptr;
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}
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void GCNHazardRecognizer::RecedeCycle() {
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llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
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}
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//===----------------------------------------------------------------------===//
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// Helper Functions
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//===----------------------------------------------------------------------===//
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int GCNHazardRecognizer::getWaitStatesSinceDef(
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unsigned Reg, function_ref<bool(MachineInstr *)> IsHazardDef) {
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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int WaitStates = -1;
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for (MachineInstr *MI : EmittedInstrs) {
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++WaitStates;
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if (!MI || !IsHazardDef(MI))
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continue;
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if (MI->modifiesRegister(Reg, TRI))
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return WaitStates;
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}
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return std::numeric_limits<int>::max();
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}
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//===----------------------------------------------------------------------===//
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// No-op Hazard Detection
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//===----------------------------------------------------------------------===//
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static void addRegsToSet(iterator_range<MachineInstr::const_mop_iterator> Ops,
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std::set<unsigned> &Set) {
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for (const MachineOperand &Op : Ops) {
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if (Op.isReg())
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Set.insert(Op.getReg());
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}
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}
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int GCNHazardRecognizer::checkSMEMSoftClauseHazards(MachineInstr *SMEM) {
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// SMEM soft clause are only present on VI+
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if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
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return 0;
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// A soft-clause is any group of consecutive SMEM instructions. The
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// instructions in this group may return out of order and/or may be
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// replayed (i.e. the same instruction issued more than once).
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//
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// In order to handle these situations correctly we need to make sure
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// that when a clause has more than one instruction, no instruction in the
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// clause writes to a register that is read another instruction in the clause
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// (including itself). If we encounter this situaion, we need to break the
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// clause by inserting a non SMEM instruction.
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std::set<unsigned> ClauseDefs;
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std::set<unsigned> ClauseUses;
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for (MachineInstr *MI : EmittedInstrs) {
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// When we hit a non-SMEM instruction then we have passed the start of the
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// clause and we can stop.
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if (!MI || !SIInstrInfo::isSMRD(*MI))
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break;
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addRegsToSet(MI->defs(), ClauseDefs);
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addRegsToSet(MI->uses(), ClauseUses);
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}
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if (ClauseDefs.empty())
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return 0;
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// FIXME: When we support stores, we need to make sure not to put loads and
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// stores in the same clause if they use the same address. For now, just
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// start a new clause whenever we see a store.
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if (SMEM->mayStore())
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return 1;
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addRegsToSet(SMEM->defs(), ClauseDefs);
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addRegsToSet(SMEM->uses(), ClauseUses);
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std::vector<unsigned> Result(std::max(ClauseDefs.size(), ClauseUses.size()));
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std::vector<unsigned>::iterator End;
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End = std::set_intersection(ClauseDefs.begin(), ClauseDefs.end(),
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ClauseUses.begin(), ClauseUses.end(), Result.begin());
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// If the set of defs and uses intersect then we cannot add this instruction
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// to the clause, so we have a hazard.
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if (End != Result.begin())
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return 1;
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return 0;
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}
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int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) {
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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int WaitStatesNeeded = 0;
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WaitStatesNeeded = checkSMEMSoftClauseHazards(SMRD);
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// This SMRD hazard only affects SI.
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if (ST.getGeneration() != SISubtarget::SOUTHERN_ISLANDS)
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return WaitStatesNeeded;
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// A read of an SGPR by SMRD instruction requires 4 wait states when the
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// SGPR was written by a VALU instruction.
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int SmrdSgprWaitStates = 4;
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auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
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for (const MachineOperand &Use : SMRD->uses()) {
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if (!Use.isReg())
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continue;
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int WaitStatesNeededForUse =
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SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
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}
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return WaitStatesNeeded;
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}
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int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) {
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const SIInstrInfo *TII = ST.getInstrInfo();
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if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
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return 0;
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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// A read of an SGPR by a VMEM instruction requires 5 wait states when the
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// SGPR was written by a VALU Instruction.
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int VmemSgprWaitStates = 5;
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int WaitStatesNeeded = 0;
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auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
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for (const MachineOperand &Use : VMEM->uses()) {
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if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
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continue;
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int WaitStatesNeededForUse =
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VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
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}
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return WaitStatesNeeded;
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}
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int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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// Check for DPP VGPR read after VALU VGPR write.
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int DppVgprWaitStates = 2;
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int WaitStatesNeeded = 0;
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for (const MachineOperand &Use : DPP->uses()) {
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if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
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continue;
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int WaitStatesNeededForUse =
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DppVgprWaitStates - getWaitStatesSinceDef(Use.getReg());
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WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
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}
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return WaitStatesNeeded;
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}
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